The Physical Design Engineer will optimize power intent and delivery networks for AI silicon, develop UPF and power grid flows, and collaborate on automated design methodologies.

Develop, optimize, and debug production ATE test programs and SSN-based scan content for high-performance AI/ML silicon. Translate ATPG patterns into production-ready tests, support silicon bring-up and manufacturing debug, collaborate with DFT/design teams, and build automation and documentation to scale test methodologies and improve yield.

As Director, Systems & Solutions, lead the deployment and optimization of AI compute systems, focusing on hardware technologies and customer engagement to enhance performance and usability.

As a Staff Design for Test STA Engineer, you will lead the definition and implementation of DFT methodologies and ensure timing closure for AI processors, collaborating with multiple teams to achieve first-pass silicon success.

Design, implement, and maintain TT-Fabric, a low-level networking library for distributed AI training/inference. Build scalable communication systems for thousands of processors, optimize protocols, synchronization, and data movement, integrate TT-Fabric APIs with programming models, and help define long-term distributed systems architecture.

Lead customer engagements focused on RISC-V CPUs and AI hardware, translating customer requirements into execution plans through coordinated SoC development programs. Ensure successful delivery while balancing customer needs with internal priorities.

The Staff Engineer will design and maintain automated OS deployment pipelines, manage configuration management, troubleshoot OS issues, and collaborate with hardware teams for HPC systems.

Own and craft high-impact slide decks that clarify complex hardware and systems ideas. Create accurate, readable infographics and diagrams, work rapidly with executives and engineers, maintain a scalable slide library, and ensure visual clarity aligned with Tenstorrent's brand.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

The role involves architecting and maintaining telemetry services, designing web GUIs for monitoring, and interfacing with engineering teams to improve observability and performance metrics.

Define and implement the MidCore block for high-performance RISC-V CPUs, collaborating with teams to ensure functional, timing, and power goals are met.

As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.

The Sr. Staff HR Business Partner will guide senior leaders in aligning talent strategies, drive complex people projects, and enhance organizational health.

As a Senior Software Engineer at Tenstorrent, you will develop AI compiler technologies, optimize computational graphs, and enhance MLIR frameworks to connect AI models with hardware.

The SoC Physical Design Verification Engineer leads full-chip signoff, ensuring high-quality silicon through physical verification and debugging across teams for successful tapeouts.

Design and build Kubernetes-based platforms for AI development and deployment, focusing on distributed systems and scalable services.

Own software functional safety for AI systems, ensuring compliance with ISO 26262. Collaborate across teams to implement safety measures in AI-driven software platforms.

The STA Methodology Engineer will lead the optimization of timing methodologies and automation, collaborating across teams to address advanced-node design challenges.

Design and validate high-speed interconnects for AI systems, defining requirements and performing reliability testing for copper and optical technologies.

As a C++ Machine Learning Engineer, you will optimize ML training frameworks, debug model performance, and collaborate with various teams to enhance model implementation.