Jobs at Tenstorrent Inc.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

As a Senior Software Engineer at Tenstorrent, you will develop AI compiler technologies, optimize computational graphs, and enhance MLIR frameworks to connect AI models with hardware.

The SoC Physical Design Verification Engineer leads full-chip signoff, ensuring high-quality silicon through physical verification and debugging across teams for successful tapeouts.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.

Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, involving hands-on infrastructure development and debugging using AI methodologies.

The role involves defining and implementing RTL for high-performance RISC-V CPUs, collaborating with various teams to ensure design meets functional, timing, and power goals while using innovative optimization techniques.

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

The STA Methodology Engineer will lead the optimization of timing methodologies and automation, collaborating across teams to address advanced-node design challenges.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

Lead cross-functional product development for AI processors and systems from concept to delivery. Drive schedules, risks, dependencies, and stakeholder alignment across hardware, software, firmware, validation, manufacturing, and suppliers. Communicate technical status to executives and coordinate structured product development processes in a hybrid, collaborative environment.

Contract HR Project Manager to operationalize People programs (promotions, performance, merit, surveys). Build plans, trackers, timelines, align stakeholders (HR, Comp, Analytics, Payroll, business leaders), track progress, surface risks, and ensure execution of cyclical high-impact work in a fast-moving environment. Hybrid role based in Santa Clara, Austin, or Toronto.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.