Jobs at Tenstorrent Inc.

Maintain reliable infrastructure across Linux systems, servers, compute clusters, and supporting systems. Monitor performance and capacity, investigate alerts, triage incidents, coordinate resolution, execute runbooks, improve dashboards and alerting, and analyze recurring failures. The role partners with infrastructure and engineering teams on root-cause analysis, automation, recovery procedures, documentation, and reliability improvements supporting AI compute platforms.

Lead logistics operations across the United States and Mexico, managing inbound, outbound, intercompany, and cross-border transportation. Oversee carriers, brokers, freight forwarders, customs brokers, and logistics providers while improving routing, shipment visibility, freight auditing, and service performance. Coordinate US-Mexico manufacturing movements, customs documentation, inventory visibility, IMMEX controls, and exception resolution. Develop SOPs, dashboards, operating reviews, and contingency plans while reducing logistics costs and maintaining service and compliance.

Owns deployment, configuration, reliability, and evolution of mixed-signal EDA environments. Develops AI-enabled automation primarily in Python with Tcl or Cadence SKILL, configures tools and PDKs, qualifies supported versions, maintains reproducible flows, and resolves workflow issues in collaboration with CAD, infrastructure, and design teams.

Drive PCIe silicon enablement from pre-silicon planning through first-silicon bring-up and product support. Develop firmware, tests, automation, and reusable infrastructure for PCIe controllers, PHYs, boards, SoCs, and SiPs. Integrate and debug root-complex and endpoint behavior, link training, equalization, resets, power management, and error recovery using lab tools and system-level investigation. Collaborate across engineering teams, define enablement and production-readiness roadmaps, mentor engineers, and improve product quality through post-silicon learnings.

Leads North American business development for AI compute solutions supporting autonomy and robotics. Builds strategic customer and industry relationships, identifies opportunities, develops partnerships and commercialization strategies, communicates technical value, advises customers, and drives regional growth, sales targets, and complex deal closure. The role requires technical credibility across AI, compute, RISC-V, hardware, robotics, and autonomous vehicles, plus collaboration with cross-functional teams to shape go-to-market strategy and product direction.

Build and scale legal operations for a growing AI and semiconductor company. Lead legal technology selection, migrations, workflow automation, commercial contract administration, NDA negotiation, KPI development, vendor and outside counsel oversight, document management, and litigation, M&A, and investor diligence support.

Build and maintain reliable infrastructure for silicon-development workloads, including simulations, verification, formal analysis, EDA, CI/CD, and repository health. Optimize performance and throughput, reduce engineering wait times, create monitored services with automated recovery, and develop AI-agent workflows for testing and debugging. Partner with hardware and software teams to resolve recurring integration failures and improve developer productivity.

Drive complex, cross-functional platform engineering initiatives across runtime systems, device drivers, deployment, observability, hardware, and architecture teams. Develop technical execution plans, manage dependencies, improve reliability and scalability, establish milestones and metrics, investigate risks, and unblock engineering progress. The role supports hardware/software integration, fleet-scale deployment, debugging, platform readiness, and engineering workflow improvements through telemetry, dashboards, automation, and AI-assisted tools.

Develop and optimize automated test equipment programs for AI and compute silicon using the Advantest V93000. Responsibilities include creating modular test and measurement libraries, implementing parametric, functional, scan, BIST, and system-level tests, debugging failures, supporting silicon characterization, extracting Vmin/Fmax, defining production limits, and improving datalogging, yield analysis, test time, multisite efficiency, and measurement stability for NPI and high-volume manufacturing.

Optimize software workloads across datacenter and agentic AI applications on RISC-V platforms. Responsibilities include profiling applications and runtimes, identifying bottlenecks, tuning compilers and runtimes, analyzing memory and concurrency behavior, leveraging vector, matrix, and custom ISA capabilities, and developing AI-assisted optimization workflows. The role collaborates across software, compiler, hardware, and performance modeling teams to improve throughput, latency, efficiency, and future CPU architecture.

Develop and apply formal verification techniques to validate high-performance RISC-V CPUs and AI compute platforms. Build properties, assertions, assumptions, constraints, coverage analyses, and formal verification environments; analyze counterexamples and debug RTL failures. Collaborate with CPU architects, RTL designers, and design verification engineers to verify complex microarchitectural behavior and resolve issues. The role requires strong SystemVerilog and SVA skills, digital design and computer architecture knowledge, and programming or scripting experience in Python, Tcl, C, or C++.

Partners with North American senior leaders on organizational design, leveling, performance calibration, investigations, reorganizations, sensitive employee matters, and exits. Diagnoses underlying organizational and people issues, guides difficult leadership decisions, and ensures fair promotion and performance practices. The role independently owns HR challenges from start to finish while helping build scalable People function systems during rapid growth.

Analyze datacenter and agentic AI workloads on next-generation RISC-V CPUs. Characterize workload behavior, identify performance bottlenecks using profiling and simulation, reduce production workloads for modeling, correlate simulations with hardware, and recommend architectural improvements. Collaborate with CPU architects, RTL designers, compiler teams, and software engineers across hardware/software boundaries to improve CPU performance, scalability, throughput, and efficiency.

Develop and scale system-level test frameworks for AI silicon in high-volume manufacturing. Build test wrappers, harnesses, abstraction layers, telemetry, logging, failure signatures, and automated triage. Integrate functional, stress, and diagnostic tests while debugging issues across hardware, firmware, drivers, operating systems, and test equipment. Collaborate with validation, manufacturing, product engineering, and silicon teams to establish reliable execution, pass/fail criteria, and data standards for yield and RMA analysis.

Designs full-custom analog and mixed-signal IC layouts for high-speed blocks and SoC integration. Responsibilities include floorplanning, placement, routing, parasitic optimization, matching, EM/IR, ESD, latch-up, and physical verification closure across advanced FinFET nodes. The engineer supports extraction and simulation and may develop automation scripts and layout methodologies. This is a remote U.S.-based role requiring collaboration with circuit designers and delivery of manufacturable silicon.

Owns full-cycle recruiting across hardware, AI software, and go-to-market roles, from hiring-manager intake through accepted offer. Responsibilities include defining job specifications and levels, assessing talent markets, designing interview loops and scorecards, advising hiring teams, tracking search metrics, influencing hiring standards, and closing senior candidates. The role is remote with global opportunities and supports recruiting process development in a growing AI hardware company.

Advise Tenstorrent during its growth phase on technology transactions and a broad range of legal matters, including intellectual property, sales, marketing, patents, trademarks, standards, business development, M&A, recruiting, and procurement. The role requires building legal processes, partnering with cross-functional teams, and supporting a regulated AI technology business.

Build and maintain performance infrastructure for RISC-V software and performance teams, including benchmarking automation, CI pipelines, workload capture, data collection, databases, dashboards, and SimPoint management. Automate workloads across silicon, FPGA, emulation platforms, and performance models. Develop QEMU- and CRIU-based checkpointing tools and collaborate with engineers to improve reproducibility and eliminate manual performance-analysis workflows.

Drive static timing analysis and timing convergence for multi-million-gate semiconductor designs on advanced process nodes. Develop constraints, timing models, closure strategies, ECOs, and automation flows; analyze violations across process corners and coordinate with Design and DFT teams through final signoff and tapeout.

Analyze and optimize multicore CPU cluster performance across caches, coherence, interconnects, memory bandwidth, latency, and scalability. Build performance models and simulations using Gem5 or equivalent, study real workloads, identify bottlenecks, lead architectural tradeoff studies, and translate performance insights into design decisions through collaboration with CPU, RTL, compiler, software, and system architecture teams.