Jobs at Tenstorrent Inc.

Analyze and optimize multicore CPU cluster performance across caches, coherence, interconnects, memory bandwidth, latency, and scalability. Build performance models and simulations using Gem5 or equivalent, study real workloads, identify bottlenecks, lead architectural tradeoff studies, and translate performance insights into design decisions through collaboration with CPU, RTL, compiler, software, and system architecture teams.

Verify high-performance RISC-V CPU cores by developing test plans, UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveform and simulation tools, identify root causes, and drive issues to closure. Collaborate with CPU architects, RTL designers, software engineers, and verification teams across architecture, microarchitecture, and the design lifecycle.

Verify the front end of high-performance RISC-V CPU cores, including instruction fetch, branch prediction, decode, dispatch, and speculative execution. Develop verification strategies, SystemVerilog/UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveforms and collaborate with CPU architects, RTL designers, and software teams to identify root causes and ensure correctness across workloads and corner cases.

Build and lead Tenstorrent’s global supply chain operating infrastructure for hardware products. Own product certification and market readiness, Sales & Operations Planning, global RMA and customer operations, scalable processes, KPIs, dashboards, governance, and cross-functional execution. The role requires developing teams, clarifying ownership, managing ambiguity, and aligning Engineering, Product, Sales, Manufacturing, Quality, Finance, Legal, customers, test labs, and regulatory bodies to support product launches and lifecycle operations.

Leads strategic sourcing for semiconductor design infrastructure, including third-party IP licensing, EDA/CAD tools, vendor negotiations, and complex technology contracts. Develops procurement strategies balancing cost, quality, delivery, and innovation; manages multiple concurrent deals; builds executive-level vendor relationships; and translates technical requirements into sourcing recommendations for leadership. The role supports global engineering teams and AI chip company scale-up operations.

Supports corporate development and strategic deal processes, including partnerships, business development, strategic sales, pipeline and CRM management, research, briefing materials, diligence, data-room organization, and executive communications. The role coordinates multiple workstreams and supports senior leadership throughout commercial transactions in the AI hardware, semiconductor, and data center ecosystems.

Defines and leads physical design methodology, automation, and signoff infrastructure for high-performance CPU cores across advanced process nodes. Owns RTL-to-GDS flows spanning synthesis, floorplanning, power planning, place and route, timing, signal integrity, EM/IR, extraction, and physical verification. Drives scalable automation, quality metrics, dashboards, and AI/ML-enabled tooling while partnering across architecture, RTL, CAD, DFT, data, program, and EDA teams.

Leads end-to-end design verification for CPU, AI accelerator, and chiplet platforms. Develops SV-UVM, C/DPI, and Cocotb simulation environments; owns test plans, coverage, regressions, failure triage, and sign-off. Collaborates with architecture, design, software, and post-silicon teams, supports emulation and multi-chip verification, and mentors junior engineers. Uses AI-assisted tools to improve verification workflows and scalability.

Lead cross-functional technical programs for AI hardware and systems from concept through production. Coordinate hardware, software, firmware, validation, manufacturing, and supplier teams; manage schedules, risks, dependencies, and stakeholder communications; align teams around shared goals; and deliver complex products on schedule.

Own and improve Finance Operations processes, controls, documentation, service levels, KPIs, and reporting. Lead root-cause analysis, corrective actions, governance, automation, systems implementations, policy rollouts, and finance transformation initiatives. Partner with Finance leadership and cross-functional technology and business teams to build scalable procedures, improve efficiency, manage change, and support responsible AI adoption in Finance.

Verify RISC-V CPU front-end units, including instruction fetch, branch prediction, caches, TLBs, and fetch control structures. Build UVM testbenches, constrained-random and directed stimulus, checkers, transactors, predictors, scoreboards, and C++ reference models. Execute verification plans, track functional and code coverage, and resolve microarchitectural edge cases with RTL, performance modeling, and software teams using simulation and emulation workflows.

Own global OSAT partnerships and backend semiconductor manufacturing from wafer-out through final shipment. Manage supplier relationships, negotiations, engineering builds, qualification lots, capacity, materials, production schedules, packaging, testing, yield, quality, logistics, and supply risks. Lead substrate and critical-material sourcing for advanced AI hardware while establishing KPI-driven processes and reliable data for analytics and automation. The role requires regular travel to Taiwan and other Asia-based partner sites.

Develop and maintain design verification tests and infrastructure for System Management Controllers in chiplet-based, multi-chip SoCs. Create and execute test plans, develop C/C++ tests for direct DUT execution, and triage and debug hardware/software issues with design and architecture teams. The role also involves SystemVerilog, SV-UVM, Python, co-simulation, advanced interconnect standards, and AI-assisted verification tools.

Own university and early-career recruiting strategy for a site, including school selection, campus partnerships, events, sourcing, screening, interview coordination, offers, and closing. Manage intern, co-op, and new-grad hiring funnels while partnering with engineering managers to define candidate profiles and maintain hiring standards. Build new-grad recruiting processes, track funnel metrics in the ATS, and improve candidate experience and recruiting outcomes through data-driven decisions.

Leads global sales and business development for an intellectual property portfolio, including strategy, licensing, partnerships, account development, negotiations, revenue growth, forecasting, and team leadership. Builds a distributed commercial organization and collaborates with engineering, legal, finance, product, and executives to monetize IP across semiconductor, AI, and hardware markets.

Lead manufacturing cost accounting including inventory, fixed assets, and COGS. Build and scale standard costing, cost roll-ups, and controls for IPO readiness. Analyze manufacturing variances, partner with Supply Chain, Sales, and R&D, and deliver COGS and margin reporting to leadership.

Build and run an enterprise sales motion for AI hardware and software: own accounts through the full lifecycle, align technical solutions to business value, collaborate cross-functionally, develop repeatable processes and materials, and manage long, complex procurement cycles to accelerate revenue.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.

Lead and scale global IT: own enterprise systems, infrastructure, security partnerships, end-user experience, and IT operations. Drive strategy, roadmaps for business applications, integrations, automation, and internal service delivery while partnering with cross-functional leaders to support rapid AI hardware and software growth.

Own multi-layer PCB layouts for high-performance AI and computing products. Route high-speed interfaces (GDDR/LPDDR/DDR, PCIe Gen5/6, Ethernet, USB), apply layout rules, select advanced fabrication (HDI, blind/buried vias, back drilling, VIPPO), collaborate with power, SI, and mechanical teams, and resolve DFM/DFA/DFT feedback to meet manufacturability and regulatory standards.