Jobs at Tenstorrent Inc.

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.

Lead architecture, development, customization, and technical oversight for core business applications and integrations (ERP, CRM, SaaS). Drive middleware and iPaaS strategy, design secure scalable APIs and microservices, manage system performance, upgrades, and risk mitigation, and provide hands-on technical leadership across integrations and cloud platforms.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

Provide strategic executive support to senior leaders in a fast-paced technical organization: manage complex calendars, communications, travel and events, and drive cross-functional initiatives to align priorities and execution.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

The engineer will focus on pre-silicon verification of DFD logic in AI SoCs, developing environments, analyzing coverage gaps, and automating testing flows.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Lead manufacturing cost accounting including inventory, fixed assets, and COGS. Build and scale standard costing, cost roll-ups, and controls for IPO readiness. Analyze manufacturing variances, partner with Supply Chain, Sales, and R&D, and deliver COGS and margin reporting to leadership.

Lead and scale global IT: own enterprise systems, infrastructure, security partnerships, end-user experience, and IT operations. Drive strategy, roadmaps for business applications, integrations, automation, and internal service delivery while partnering with cross-functional leaders to support rapid AI hardware and software growth.

Own multi-layer PCB layouts for high-performance AI and computing products. Route high-speed interfaces (GDDR/LPDDR/DDR, PCIe Gen5/6, Ethernet, USB), apply layout rules, select advanced fabrication (HDI, blind/buried vias, back drilling, VIPPO), collaborate with power, SI, and mechanical teams, and resolve DFM/DFA/DFT feedback to meet manufacturability and regulatory standards.

Develop and maintain infrastructure platforms for AI services, build APIs, manage Kubernetes clusters, and automate workflows using CI/CD practices.

Select and qualify electronic components for high-performance AI compute systems, maintain Approved Vendor List, drive multi-sourcing and cost optimization, monitor lifecycle and supplier risk, and collaborate with hardware, procurement, and supply teams to ensure component availability for scalable production.

Lead and deliver agentic workflow and program intelligence initiatives: define opportunities, structure ambiguous work into programs, integrate systems and data pipelines, drive automation, partner with engineering, infrastructure, and data teams, and produce executive-ready reporting.

The Risc-V Architect will analyze AI workloads, design custom RISC-V cores, and lead the architecture efforts at Tenstorrent, improving CPU performance.

Physical Design Engineers at Tenstorrent are responsible for implementing high-performance AI SoC designs, overseeing the complete implementation flow from synthesis to tapeout and collaborating with cross-functional teams to ensure all design aspects are met.

Own end-to-end electronics components and PCB supply chain, managing suppliers (CMs, PCB fabs, distributors), supporting NPI and production ramps, aligning forecasts, negotiating multi-year contracts, and mitigating supply risks to ensure product availability and revenue.