Teams at Tenstorrent Inc.

Analyze and optimize multicore CPU cluster performance across caches, coherence, interconnects, memory bandwidth, latency, and scalability. Build performance models and simulations using Gem5 or equivalent, study real workloads, identify bottlenecks, lead architectural tradeoff studies, and translate performance insights into design decisions through collaboration with CPU, RTL, compiler, software, and system architecture teams.

Verify high-performance RISC-V CPU cores by developing test plans, UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveform and simulation tools, identify root causes, and drive issues to closure. Collaborate with CPU architects, RTL designers, software engineers, and verification teams across architecture, microarchitecture, and the design lifecycle.

Verify the front end of high-performance RISC-V CPU cores, including instruction fetch, branch prediction, decode, dispatch, and speculative execution. Develop verification strategies, SystemVerilog/UVM testbenches, constrained-random tests, assertions, and functional coverage. Debug RTL and simulation failures using waveforms and collaborate with CPU architects, RTL designers, and software teams to identify root causes and ensure correctness across workloads and corner cases.