Jobs at Velaura AI, Inc.

Own the architecture and technical direction of a heterogeneous AI SoC runtime spanning sensor ingest, preprocessing, inference, postprocessing, and application delivery. Define execution, memory, synchronization, driver, firmware, compiler-runtime, observability, resilience, and validation architectures. Lead cross-functional engineers while contributing hands-on to production systems software, performance optimization, APIs, and low-level interfaces for robotics and edge AI workloads.

Own verification of custom AI accelerator hardware, including matrix and vector engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regressions. Verify numerical precision, quantization, data flow, performance, latency, and power efficiency across RTL blocks and complete systems. Collaborate with architecture, software, compiler, runtime, and systems teams through design bring-up, emulation, and pre-silicon validation.

Own the CAD and engineering infrastructure supporting silicon development, including compute, storage, scheduling, cloud, security, disaster recovery, EDA tools, licensing, and RTL-to-GDS flow releases. Lead CI/CD, regression infrastructure, flow qualification, vendor strategy, and AI-assisted engineering adoption. Ensure scalable, reproducible, secure platforms support concurrent SoC programs and thousands of weekly jobs while partnering with RTL, verification, DFT, physical design, packaging, and software teams.

Serves as the first point of contact for the office while managing reception, visitors, mail, packages, conference rooms, supplies, vendors, invoices, workplace inventory, interviews, events, onboarding, and general administrative support. The role requires strong organization, communication, discretion, and proficiency with office productivity, calendar, collaboration, and video-conferencing tools.

Leads the architecture and development of customer-facing SDKs, APIs, CLI tools, examples, documentation, developer workflows, and portal integrations for an AI SoC platform. Partners across AI, multimedia, robotics, tools, release, and SQA teams to deliver reliable installation, deployment, compatibility, and release experiences. The role also hires, mentors, and leads engineers focused on developer tools, documentation systems, APIs, and sample applications.

Develop system-level performance models and simulation frameworks for AI workloads, software runtimes, and hardware architectures. Model SoC components, memory systems, and interconnects; analyze bottlenecks and architectural tradeoffs; and evaluate latency, throughput, scalability, and energy efficiency. Collaborate with hardware architects, software engineers, and ML teams to support hardware-software co-design and guide next-generation AI compute platform decisions.

Design and verify Velaura’s next-generation Physical AI SoC from RTL blocks through full hardware and software systems. Responsibilities include building SoC simulation environments, verifying boot, root of trust, clock/reset, low-power, IO and memory subsystems, running CDC/RDC analysis, evaluating performance and QoS, and supporting coverage closure, signoff, and tape-out. The role also involves hardware-software co-verification, emulation, FPGA prototyping, and post-silicon debugging.

Design and optimize RTL for a high-speed, low-power SoC memory subsystem, including memory controllers, PHY integration, DFI interfaces, training, calibration, power management, scheduling, ECC, and performance optimization. Collaborate with architecture, software, verification, physical design, IP, and PHY teams through silicon bring-up. The role requires deep expertise in Verilog/SystemVerilog, memory technologies, computer architecture, and low-power digital design.

Design and optimize RTL for key portions of a high-performance, power-efficient SoC. Collaborate with architects, software, verification, and physical design teams on microarchitecture, hardware/software interfaces, memory systems, interconnects, compute engines, DMA, and power-management logic. Analyze performance, power, and area tradeoffs, resolve bottlenecks, and contribute to production silicon development for Physical AI applications.

Lead architecture, transistor-level design, optimization, and verification of high-performance, low-power standard cells and custom digital circuits for advanced AI and HPC silicon. Own PPA optimization, arithmetic circuit development, statistical and reliability verification, layout collaboration, characterization, ASIC sign-off, methodology improvements, and silicon readiness. Mentor engineers and provide technical leadership across circuit design and advanced semiconductor development.

Own and scale formal verification for complex SoC blocks, including CPUs, floating-point units, vector engines, and datapaths. Develop SVA properties, formal testbenches, constraints, abstractions, equivalence checks, and coverage strategies. Debug counterexamples, close difficult proofs, and build reusable formal applications. Partner with architecture, RTL, and simulation teams while maintaining automation, CI, regressions, and proof tracking. Apply formal methods to arithmetic correctness, protocols, security, low-power, CDC/RDC, and AI hardware verification.

Develop and execute verification strategies for a next-generation Physical AI SoC. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify digital blocks, memory systems, interconnects, processors, DMA engines, and complete HW/SW behavior. Perform performance, latency, QoS, emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Lead system-level design verification for a next-generation Physical AI SoC from verification planning through sign-off and tape-out. Own verification architecture, coverage goals, regressions, and risk tracking while coordinating boot, security, clock/reset, low-power, IO, and memory subsystem verification. Build and guide a verification team, remain hands-on in SystemVerilog and UVM, and partner with architecture, RTL, firmware, software, CAD, and infrastructure teams on simulation, emulation, and pre-silicon bring-up.

Leads IT infrastructure and operations across hybrid cloud, on-premises, HPC, engineering compute, storage, networking, security, CI/CD, and employee technology. Owns capacity planning, disaster recovery, IAM, endpoint security, compliance readiness, service desk operations, budgets, vendors, and facilities technology. Manages and grows the IT team while supporting semiconductor and AI engineering workloads, protecting design IP, and ensuring infrastructure readiness for tape-outs and product releases.

Own front-end semiconductor design and verification automation from RTL entry through DFT and implementation handoff. Responsibilities include RTL build, lint, CDC, formal, register generation, simulation, regressions, coverage, emulation, FPGA prototyping, and AI-assisted tooling. The role also manages EDA tool versions, distributed compute, flow health, maintenance, and collaboration with design, verification, DFT, and physical design teams.

Design and optimize RTL for key portions of a next-generation Physical AI SoC. Own significant blocks through microarchitectural definition, implementation, optimization, and tapeout while collaborating with architecture, software, verification, and physical design teams. Contribute to compute engines, memory subsystems, interconnects, DMA, control processors, and power-management logic. Analyze performance, power, and area tradeoffs, lead design reviews, debug complex systems, and mentor junior engineers.

Define and build the software architecture underlying Velaura’s Physical AI platform, including SDKs, runtimes, drivers, firmware, compilers, developer tools, and workload orchestration. Lead hardware/software co-design, performance optimization, profiling, and integration with ROS2, DDS, robotics, drones, and autonomous systems. Establish engineering processes and help develop a high-performing platform software team enabling efficient AI deployment across heterogeneous computing systems.

Administer and improve enterprise infrastructure across Linux, Windows, macOS, cloud, virtualization, networking, storage, backup, identity, and endpoints. Develop automation, maintain secure configurations, monitor systems, remediate vulnerabilities, investigate incidents, and support compliance initiatives. Provide Tier 2/3 desktop engineering, device provisioning, onboarding and offboarding, endpoint management, troubleshooting, and documentation. Collaborate with engineering, security, and operations teams to deliver reliable, scalable, and secure infrastructure.

Lead RTL development for a next-generation Physical AI SoC, translating system architectures into production-quality microarchitectures and silicon. Responsibilities include hardware/software co-design, compute and memory subsystem design, interconnect and control logic, performance-power-area optimization, architecture and RTL reviews, cross-functional collaboration, process development, and mentoring RTL engineers. The role requires deep digital design expertise, Verilog/SystemVerilog experience, complex SoC development, and full-cycle ownership through silicon bring-up.

Own the functional safety architecture and lifecycle for Physical AI SoCs, from early architecture through tape-out, qualification, and production. Lead hazard analysis, FMEDA, FTA, fault analysis, safety metrics, and safety mechanisms across compute, AI accelerators, memory, and interconnects. Define hardware/software safety requirements, safety cases, and SEooC assumptions; coordinate certification and audits; establish safety processes; and mentor cross-functional silicon, firmware, software, and product teams.