passionate about building great hardware and solving challenging technical problems.
- Responsibilities
● Design, implement, and optimize RTL for key portions of the Velaura SoC.
● Collaborate with architects to develop robust and efficient microarchitectures.
● Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
● Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
● Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
● Optimize designs for performance, power, area, scalability, and reliability.
● Partner closely with verification and physical design teams throughout the development cycle.
● Analyze performance bottlenecks and propose architectural and implementation improvements.
● Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
● Participate in design reviews and contribute to a culture of technical excellence.
● Experience designing RTL for complex digital systems.
● Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
● Experience with Verilog/SystemVerilog and modern RTL design methodologies.
● Familiarity with performance, power, and area tradeoffs.
● Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
● Experience with hardware/software co-design and system-level performance optimization.
● Strong debugging and problem-solving skills.
● Ability to work effectively in a collaborative, multidisciplinary engineering environment.
- Preferred Qualifications
● Experience with AI, machine learning, or edge AI hardware.
● Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
● Knowledge of low-power design techniques and power management architectures.
● Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
● Experience using modern AI tools and workflows to accelerate engineering productivity.
● Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS),
aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.
Velaura is building next-generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.
This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.
Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment
opportunities to minorities, women, individuals with disabilities, and protected veterans.
Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact
information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.
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