ASIC DFT Engineer

Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for APD's designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

Responsibilities:

• Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC

• Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration

• Responsibilities includes pattern generation & Verification at chip level, Rapid bring-up at ATE and RMA support

• Working closely with STA and DI Engineers design closure for test

• Generating, Verifying & Debugging Test vectors before tape release.

• Validating & Debugging Test vectors on ATE during the silicon bring up phase

• Assisting with silicon failure analysis, diagnostics & yield improvement efforts

• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally

• Working closely with I/P DFT engineers & other stakeholders

• Debugging customer returned parts on the ATE

• Innovating newer DFT solutions to solve testability problems in 3nm & beyond

• Automating DFT & Test Vector Generation flows

Skills/Experience:

• Bachelors and 12+ years of related experience; or Masters degree and 10+ years of related experience

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)

• Logic BIST design and debug experience

• Well-versed in ATPG vector generation, simulation, and  debugging. (TetraMax, Fastscan)

• Experience in Verilog coding, testbench generation & simulation

• Memory BIST insertion and verification experience on embedded  (SRAM, CAM, eDRAM, ROM)

• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6

• Basic knowledge Test-STA and constraints

• Strong background on IEE1687, IJTAG, ICL and PDL 

• The ability to work in a multi-disciplined, cross-department environment

• Solid knowledge in analog and digital circuit design, and device physics fundamentals

• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

• Excellent problem solving, debug, root cause analysis and communication skills

• Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics

• Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations.

• Experience working on ATE is a plus

• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus

• Experience working on Tessent SSN is a plus