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Etched

Chip Simulation Software Engineer

Reposted 3 Days Ago
In-Office
San Jose, CA
200K-250K Annually
Mid level
In-Office
San Jose, CA
200K-250K Annually
Mid level
Design and develop simulations for a custom chip in a collaborative environment, focusing on accuracy and performance. Requires strong software and hardware engineering skills.
The summary above was generated by AI

About Etched

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking highly motivated and detail-oriented software engineers to join our chip simulation team. We’re building Sohu, the world’s first transformer ASIC that leverages tight hardware-software co-design to deliver world-best performance. The chip simulation team plays a key role in hardware-software co-design, enabling early development of the full Sohu software stack. As a software engineer on this team, you will design, develop, and test simulations of our custom hardware systems. You will be working at the cutting edge of hardware innovation, ensuring that our software and hardware teams are able to closely coordinate on their development paths.

Key responsibilities

  • Simulation Development: Design, develop, and maintain simulations of our hardware. Ensuring high levels of accuracy, efficient debugging, and optimal performance.

  • Documentation: Create and maintain test plans, work with hardware teams to validate their documentation.

  • Debug tooling: Build tools to debug simulations, and enable developers to debug software running on the simulator.

  • Cross-functional Collaboration and Troubleshooting: Chip simulation engineers are expected to work closely with both hardware and software engineers to make sure that our simulations are accurate, and that software engineers are able to use them with a high level of productivity.

You may be a good fit if you have

  • Proficiency in C/C++

  • Strong understanding of low-level software engineering.

  • Strong understanding of hardware engineering.

  • Excellent communication and collaboration skills.

Strong candidates may also have

  • Experience developing hardware or system simulations (e.g., SystemC, gem5, QEMU, or custom frameworks).

  • Experience with custom ML hardware accelerators (e.g., Google TPU)

  • Experience with firmware, kernel and driver development (e.g., Linux, FreeRTOS)

  • Experience with hardware development and verification.

  • Experience with multiprocessing and multithreading.

  • Familiarity with bit-accurate numerics modeling.

  • Experience with performance profiling and optimization of simulation code

  • Proficiency with Python for test harness development, bazel, and git.

Representative projects

  • Implement a simulation of Sohu’s on-chip modules.

  • Integrate simulated chips with simulated hosts (QEMU), enabling Kernel driver development and host software testing.

  • Integrate multiple simulated chips to validate multi-chip software scale-out and scale-up approaches.

  • Work closely with Sohu software teams in debugging early software deliverables.

Benefits

  • Full medical, dental, and vision packages, with generous premium coverage

  • Housing subsidy of $2,000/month for those living within walking distance of the office

  • Daily lunch and dinner in our office

  • Relocation support for those moving to San Jose (Santana Row)

Base Salary Compensation

  • $200,000 - $250,000

How we’re different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Top Skills

Bazel
C/C++
Freertos
Gem5
Git
Linux
Python
Qemu
Systemc
HQ

Etched Cupertino, California, USA Office

Cupertino, CA, United States

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