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SiFive

CPU Design Intern

Posted Yesterday
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In-Office
Santa Clara, CA, USA
32K-39K Hourly
Internship
In-Office
Santa Clara, CA, USA
32K-39K Hourly
Internship
As a CPU Design Intern, you will develop RTL for RISC-V cores, gain knowledge in computer architecture, and work on performance and power optimization.
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About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

Are you ready?  

To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

 

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
What You Will Work On
As an Intern on the Out-of-Order Core/Cache Design team, you will develop RTL for SiFive’s flagship RISC-V core series using the Chisel hardware description language. Specific projects will depend on the interests of the candidate, but may include RTL feasibility experiments, power analysis/reduction, performance enhancements, and/or designing/improving small logic modules.
What You Will Learn
  • Digital logic and RTL design principles.
  • The Chisel hardware design generator language.
  • High-performance CPU micro-architecture, power analysis and optimization techniques.
  • How to work as part of a tight-knit, agile team that stresses good design, documentation, verification testing, and code review practices.
Requirements
  • Pursuing a Master's or PhD in Computer Engineering, Computer Science, Electrical Engineering, or a similar discipline.
  • Familiarity or academic experience with Chisel, or at least Object Oriented Programming or functional programming, is strongly preferred.
  • Advanced academic understanding of Computer Architecture, Out-of-Order CPU Micro-architecture, Caches, and RTL design.

Pay & Benefits

Consistent with SiFive values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

$32.40-$39.00

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in

United States of America

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.

Top Skills

Chisel
Digital Logic
Functional Programming
Object Oriented Programming
Risc-V
Rtl
HQ

SiFive San Mateo, California, USA Office

1875 S Grant St, San Mateo, CA, United States, 94402

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