Design Verification Engineer - Memory Controller IP

Job Overview
Join the Memory Controller IP verification team as a Design Verification Engineer and help deliver reliable IP for next-generation memory technologies. You will develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behaviour across supported memory technologies. Collaborating with RTL designers, architects, and verification colleagues, you will investigate complex issues, support verification closure for assigned features, and contribute to the delivery of high-quality IP.
Responsibilities

• Develop and maintain SystemVerilog/UVM verification environments for Memory Controller IP.
• Create verification plans, test scenarios, assertions, functional coverage models, and scoreboards from architectural specifications.
• Develop constrained-random and directed tests to verify memory controller functionality across supported LPDDR and DDR technologies.
• Analyse regressions, coverage, simulation waveforms, and logs to identify and resolve RTL, testbench, and protocol issues.
• Partner with RTL designers, architects, and verification teams to clarify behaviour, resolve issues, and support verification sign-off.
• Improve verification efficiency through scripting, automation, and verification methodology improvements.
• Take ownership of assigned features and deliver verification milestones to agreed schedules.

Required Skills and Experience

• Practical experience verifying ASIC or SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.
• Ability to develop verification plans and translate architectural specifications into tests, coverage, and verification environments.
• Understanding of memory controller architecture and memory protocol concepts, including LPDDR or DDR technologies.
• Ability to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs, and communicate findings clearly with cross-functional teams.

Nice-to-Have Skills and Experience

• Experience with LPDDR5, LPDDR6, DDR5, DDR6, or other memory technologies.
• Knowledge of DFI interfaces, including DFI 4.x or 5.x.
• Familiarity with AMBA protocols such as AXI, ACE, or CHI.
• Experience with simulation and debug tools such as Synopsys VCS or Siemens Questa.
• Experience improving verification workflows through scripting, automation, or methodology development.

In Return
This role offers the opportunity to work on Memory Controller IP that supports evolving memory technologies and complex SoC designs. You will collaborate with specialists across RTL design, architecture, and verification while building deeper expertise in verification strategy, protocol analysis, coverage closure, and debugging. Your work will have a direct impact on the quality and readiness of assigned IP features and on how the team improves its verification approach.
Additional Information
Please note that no relocation package is available for this role.
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Salary Range:
$249,900-$338,100 per year
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