Functional Verification Engineer - Applying LLMs for Chip Design

About Us

Chips are at the center of today's tech-driven world. But how we design them has not changed in decades, while their complexity and specialization have skyrocketed due to increasing performance demands from applications like AI. We want to change that.

Our team is small, technical, and fast-moving. We’ve built and shipped at the intersection of AI, EDA, and systems software, with deep roots at companies like Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI. We’re backed by top investors including Khosla Ventures, Cerberus, and Clear Ventures, and already deployed with 10+ innovative customers—from Fortune 100s to cutting-edge AI silicon startups.

Position Overview

We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in developing UVM test benches and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment.

Key Responsibilities

• Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like UVM.

• Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.

• Identify and address common challenges in UVM-based verification by designing and implementing AI driven solutions.

• Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.

• Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

• Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

• Proven expertise of more than 3 years in digital design (RTL/FPGA/ASIC) and verification methodologies such as UVM and OVM.

• Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.

• Hands-on experience with industry standard EDA tools (e.g., Cadence, Synopsys) and familiarity with AI enabled design flows.

• Strong programming skills in Verilog/VHDL, System Verilog and Python

• Excellent communication skills and the ability to thrive in a team-oriented environment.

• Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.

Why Join Us?

As a young startup funded by top VCs in Silicon Valley, this is a unique opportunity that you can’t really get anywhere else:

• Personal impact — The opportunity to build something from the ground up and define a new product for an industry that is at the core of the modern technological revolution.

• Access to unique learning opportunities — With the Allen Institute for AI (AI2) as a co-founder, our team gets access to numerous talks by leading AI researchers/paper authors, knowledge sharing amongst the community of hundreds of engineers working for AI2 companies, and much more. As a part of the multi-disciplinary team, you get to interact with people from very different backgrounds (from chip design to AI to software engineers).

• Founding title — You will be one of our first hires. For the rest of our days, no matter how many thousands of people join after you, you will always have that honor and distinction.

• Early-stage equity — Early-stage risk comes with early-stage equity for you. And none of us would be here if we didn’t think our company would create tremendous value over time.

• Benefits — In spite of being an early-stage company, taking care of our team is a priority for us. From health insurance to catered lunches, we continue to add unique benefits.