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Foundation Robotics

Principal Compute Architect

Reposted 4 Days Ago
Be an Early Applicant
In-Office
San Francisco, CA, USA
80K-1M Annually
Senior level
In-Office
San Francisco, CA, USA
80K-1M Annually
Senior level
Lead technical evaluations for custom inference chips in robotics, analyze bottlenecks, define architecture, and guide RTL prototyping while delivering reports with strategic recommendations.
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About Us


Foundation is developing the future of general purpose robotics with the goal to address the labor shortage.


Our mission is to create advanced robots that can operate in complex environments, reducing human risk in conflict zones and enhancing efficiency in labor-intensive industries.


We are on the lookout for extraordinary engineers and scientists to join our team. 


Your previous experience in robotics isn't a prerequisite — it's your talent and determination that truly count.


We expect that many of our team members will bring diverse perspectives from various industries and fields. We are looking for individuals with a proven record of exceptional ability and a history of creating things that work.


Our Culture


We like to be frank and honest about who we are, so that people can decide for themselves if this is a culture they resonate with. Please read more about our culture here https://foundation.bot/culture.


Who should join:

  • You like working in person with a team in San Francisco.
  • You deeply believe that this is the most important mission for humanity and needs to happen yesterday.
  • You are highly technical - regardless of the role you are in. We are building technology; you need to understand technology well.
  • You care about aesthetics and design inside out. If it's not the best product ever, it bothers you, and you need to “fix” it.
  • You don't need someone to motivate you; you get things done.
Why are We Hiring for this Role:
  • Leading a structured evaluation of technical and business feasibility for a custom inference chip tailored to robotic workloads.
  • Analyzing current bottlenecks in robotic inference pipelines and comparing off-the-shelf vs. custom alternatives.
  • Developing models for performance, cost, scalability, power, and area to inform build-vs-buy decisions.
  • Defining high-level chip architecture optimized for low-latency, real-time systems (e.g., CNNs, transformers, sensor fusion).
  • Evaluating tradeoffs in dataflow, memory hierarchy, interconnects, and hardware/software interfaces.
  • Guiding RTL prototyping, simulation, and early design exploration.
  • Coordinating with external vendors, foundries, or design houses as needed.
  • Delivering a comprehensive report with recommendations, including technical/financial analysis and risk/benefit tradeoffs.
  • Presenting findings to leadership and, if approved, leading early custom IC design and project planning.


What Kind of Person We Are Looking For:

  • Proven track record in designing or evaluating AI accelerators, neural network inference engines, or signal processing hardware, with a history of delivering end-to-end projects.
  • Deep expertise in hardware/software co-design, embedded compute tradeoffs, and optimizing for real-time, low-power systems.
  • Hands-on experience with RTL design (Verilog/VHDL/SystemVerilog), simulation, synthesis tools, and ASIC/FPGA development.
  • Ability to model and evaluate AI inference workloads, including performance bottlenecks and architectural tradeoffs.
  • Strong leadership and communication skills to translate complex technical insights into actionable executive recommendations.
  • Experience in robotics, autonomous systems, edge computing, or similar high-stakes environments where scrappiness was key to success.
  • Familiarity with low-power design, mixed-signal integration, hardware security, chip bring-up, verification, and validation.
  • Prior collaboration with foundries, ASIC vendors, or design houses in resource-constrained settings.
  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of experience in digital IC design, SoC architecture, or ASIC/FPGA development, with demonstrated ability to own projects autonomously.

Benefits


We provide market standard benefits (health, vision, dental, 401k, etc.). Join us for the culture and the mission, not for the benefits.


Salary


The annual compensation is expected to be between $180,000 - $300,000. Exact compensation may vary based on skills, experience, and location.


Top Skills

Ai Accelerators
Asic
Fpga
Hardware/Software Co-Design
Rtl Design
Systemverilog
Verilog
Vhdl
HQ

Foundation Robotics San Francisco, California, USA Office

617 Bryant St, San Francisco, California, United States, 94107

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