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HP IQ

Lead RF Systems and Desense Engineer

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In-Office
San Francisco, CA, USA
180K-270K Annually
Expert/Leader
In-Office
San Francisco, CA, USA
180K-270K Annually
Expert/Leader

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Lead RF system architecture, integration, and desense mitigation for wearable/mobile products across Wi‑Fi, Bluetooth, UWB and NFC. Define specs, run CST/ADS simulations, review PCB layouts, lead RF bring‑up and OTA/conducted validation, support certifications, mentor engineers, and drive cross‑functional RF performance decisions from concept through mass production.
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Who We Are

HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates.

We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—focused on creating an intelligent ecosystem across HP’s portfolio. Together, we’re developing intuitive, adaptive solutions that spark creativity, boost productivity, and make collaboration seamless.

We create breakthrough solutions that make complex tasks feel effortless, teamwork more natural, and ideas more impactful—always with a human-centric mindset.

By embedding AI advancements into every HP product and service, we’re expanding what’s possible for individuals, organisations, and the future of work.

Join us as we reinvent work, so people everywhere can do their best work.

About The Role

HP IQ's Wireless Technology Team works cross-functionally with Electrical Engineering, Software, Mechanical Engineering, Product Design, Industrial Design, Program Management, and Operations to develop next-generation wearable and AI-connected products. 

As a Lead RF Systems & Desense Engineer, you will own the RF system architecture from concept through mass production. You will lead RF integration across Wi-Fi, Bluetooth, UWB, NFC and emerging wireless technologies while driving RF desense, coexistence, and wireless performance for highly integrated products. 

What You Might Do

  • Lead RF system architecture and integration for wearable and mobile platforms.
  • Own RF desense investigations and mitigation across the product lifecycle.
  • Define RF specifications, link budgets, validation plans and performance targets.
  • Lead coexistence strategy for Wi-Fi, Bluetooth, UWB, NFC and other radios.
  • Partner with antenna, EE, FW, ME and silicon vendors to optimize total wireless performance.
  • Perform CST and ADS simulations for RF front-end, coupling and matching optimization.
  • Review PCB layouts for RF routing, grounding, shielding and isolation.
  • Lead RF bring-up, characterization, tuning and root-cause analysis.
  • Drive OTA and conducted validation including TRP, TIS, sensitivity, EVM, throughput and coexistence.
  • Support FCC, CE, Wi-Fi Alliance, Bluetooth SIG, FiRa and NFC Forum certifications.
  • Mentor engineers and establish RF design guidelines and best practices. Present technical recommendations to executive leadership. 

Essential Qualifications

  • 10+ years developing RF systems for high-volume consumer electronics, wearables or mobile products.
  • Expertise in RF fundamentals including impedance matching, S-parameters, link budgets, EVM, noise figure, linearity and receiver sensitivity.
  • Deep expertise in RF desense analysis and mitigation.
  • Strong knowledge of RF coexistence mechanisms and mitigation techniques.
  • Expert understanding of Wi-Fi (802.11 a/b/g/n/ac/ax/be), Bluetooth Classic & LE, UWB and NFC.
  • Hands-on experience with RF front-end design including PAs, LNAs, FEMs, filters, switches and matching networks.
  • Expertise using CST Studio Suite and Keysight ADS.
  • Hands-on experience with VNA, spectrum analyzer, vector signal analyzer, signal generators and OTA chambers.
  • Strong understanding of EMI/EMC, PCB layout, grounding and shielding. 

Preferred Skills

  • Python or MATLAB automation.
  • Cadence Allegro or equivalent PCB tools.
  • Experience working with Qualcomm, NXP, Broadcom or Nordic.
  • Knowledge of wearable RF architectures and compact antenna integration.
  • Experience mentoring engineers and leading cross-functional architecture decisions.
  • Excellent debugging, communication and technical leadership skills. 

Salary range: $180,000 - $270,000

Compensation & Benefits (Full-Time Employees)

The salary range for this role is listed above. Final salary offered is based upon multiple factors including individual job-related qualifications, education, experience, knowledge and skills.

At HP IQ, we offer a competitive and comprehensive benefits package, including:

  • Health insurance
  • Dental insurance
  • Vision insurance
  • Long term/short term disability insurance
  • Employee assistance program
  • Flexible spending account
  • Life insurance
  • Generous time off policies, including; 
    • 4-12 weeks fully paid parental leave based on tenure
    • 11 paid holidays
    • Additional flexible paid vacation and sick leave (US benefits overview)

Why HP IQ?

HP IQ is HP’s new AI innovation lab, building the intelligence to empower humanity—reimagining how we work, create, and connect to shape the future of work.

  • Innovative Work
    Help shape the future of intelligent computing and workplace transformation.
  • Autonomy and Agility
    Work with the speed and focus of a startup, backed by HP’s scale.
  • Meaningful Impact
    Build AI-powered solutions that help people and organisations thrive.
  • Flexible Work Environment
    Freedom and flexibility to do your best work.
  • Forward-Thinking Culture
    We learn fast, stay future-focused, and imagine what comes next—together.

Equal Opportunity Employer (EEO) Statement

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s).

Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence.

If you’d like more information about HP’s EEO Policy or your EEO rights as an applicant under the law, please click here: Equal Employment Opportunity is the Law Equal Employment Opportunity is the Law – Supplement

HQ

HP IQ Palo Alto, California, USA Office

1501 Page Mill Road, Palo Alto, United States, 94304

HP IQ San Jose, California, USA Office

San Jose, United States

HP IQ Sunnyvale, California, USA Office

Sunnyvale, United States

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Key Facts About San Francisco Tech

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  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
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