Layout Engineer

The DRAM Engineering Group (DEG) at Micron is dedicated to innovating and optimizing memory solutions. Our team designs and analyzes digital and analog circuits, collaborating globally to deliver high-performance, cost-effective, and reliable DRAM products that meet the demands of modern computing. Layout Team Mission: Build precise, high-quality, reliable layouts on time, every time – while fostering development, sharing knowledge, and innovating as one team.

As a Layout Engineer in DEG, you will translate schematics into manufacturable layouts that meet design intent, process rules, and schedule commitments for advanced DRAM. You’ll work closely with Design, Process Integration, and CAD teams to floorplan, implement, and verify custom digital, memory, and analog circuits – and help us continuously improve methods, automation, and documentation so others can follow. You will play a crucial role in developing layouts for critical custom, memory, analog, or standard cell circuits, ensuring predictable, on‑time delivery of memory designs.

Responsibilities:

• Design and Development: Create layout designs for critical circuits, ensuring compliance with process rules and schematic intent. Work closely with Design, Process, and CAD engineers to deliver solutions from floorplan through final design.

• Layout Verification: Perform verification tasks such as LVS (Layout vs. Schematic), DRC (Design Rule Check), and quality checks. Continuously improve verification tools and methodologies to ensure high‑quality layouts.

• Methods, Automation & Documentation: Tackle ambiguous problems; prototype solutions without a playbook; then codify them into guides/SOPs and share with the team. Contribute scripts (e.g., SKILL/Python) and layout method improvements to advance automation and drive measurable productivity gains. Integrate automated layout solutions to shape the future of layout design.

• On‑Time Delivery: Coordinate with global partners to meet predictable schedules and support tapeout/mask generation processes. Deliver block‑level layouts within specified timelines while maintaining quality standards.

• Project Management: Lead layout planning for assigned blocks or sub‑projects; coordinate priorities, provide guidance to other engineers, and ensure schedule alignment. Mentor team members on layout techniques, verification protocols, and tool usage.

Minimum Qualifications:

• PhD in Electrical/Computer Engineering or related major.

• Familiarity in layout tools and methodologies, including Cadence Virtuoso VXL and Calibre for DRC/LVS/Verifications.

• Exposure to semiconductor custom/memory/analog layout.

• Solid understanding of CMOS processes, design rules, and layout‑dependent effects.

• Proven problem‑solving in ambiguity with high attention to detail and quality.

Preferred Qualifications:

• Semiconductor custom/memory/analog layout experience with demonstrated block/project leadership, including mentoring and schedule management.

• DRAM/LPDDR/HBM memory product layout background; familiarity with tapeout/mask generation flows.

• Scripting (SKILL, Python) and experience building methodology/automation.

• Strong collaboration skills across global, multi-functional teams; excellent written documentation abilities.