Efficient Computer Logo

Efficient Computer

Performance Research Engineer (multiple levels)

Reposted 9 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
180K-250K Annually
Expert/Leader
In-Office
San Jose, CA, USA
180K-250K Annually
Expert/Leader
Research and develop performance optimization techniques, AI-assisted optimization tools, and performance analysis for a novel fabric dataflow processor. Design and run simulator-based experiments, collaborate with architecture and compiler teams to influence ISA and code generation, and integrate optimizations into performance libraries and resource-constrained runtime environments.
The summary above was generated by AI

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution

About the Role

We are seeking Performance Research Engineers (staff to principal levels) to join our growing team. Efficient’s Performance Research Engineers research new optimization techniques; design new tools for AI assisted optimization and performance analysis;  collaborate with our architecture team on the design of future hardware;  design and perform modeling experiments using our architecture simulator; and collaborate with our world class compiler team, evaluating code-generation quality, suggesting new intrinsics, influencing the ISA, and experimenting with new language extensions.    This is an applied research role, where you will be asked to drive the integration of these new techniques, tools, and language extensions into our existing performance libraries. 

This position is a unique opportunity to work on cutting-edge hardware/software co-design, while making an immediate impact on building the next generation of performance libraries, applications, and hardware used by our customers.

Required Qualifications & Experience
  • Hands-on software development experience working closely with hardware, including exposure to at least two RISC, DSP or GPU platforms.  
  • A  passion for understanding and addressing performance issues that are unique to our Fabric dataflow architecture.
  • Experience with  framework and library design, particularly within resource constrained and realtime environments.
  • Experience with CUDA, HIP and/or other parallel programming models.
  • The ability to lead and work independently.
  • A collaborative spirit, with the ability to work with and influence multiple engineering teams.
  • Demonstrated ability to write, debug, and maintain low-level, C/C++, systems-level code as well as design clean interfaces and modular code.
  • Actively uses AI tools to generate, optimize, and debug code.
  • Familiarity with low-level programming interfaces, e.g. PTX, LLVM IR and/or MLIR. 
  • Experience working with HW simulation environments.
  • Domain expertise in three or more of the following areas:  Linear Algebra, ML, Image Processing, Video Processing, Signal Processing, Audio Processing, SDR, realtime programming, or Robotics.
  • Background in performance profiling, benchmark design, or comparative hardware analysis.
  • Excellent written, verbal, analytical and technical communication skills, with the ability to clearly document complex systems,  lead discussions across teams, as well as the ability to drive consensus across teams.
  • Minimum Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.   PHD preferred.  Equivalent work experience.
Desired Qualifications & Experience
    • Some experience working on compiler development.
    • Some experience working with high-performing HW architecture teams.

We offer a competitive salary for this role, generally ranging from $180,000 to $250,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.

Why Join Efficient?

Efficient offers a competitive compensation and benefits package, including 401K match, company-paid benefits, equity program, paid parental leave, and flexibility. We are committed to personal and professional development and strive to grow together as people and as a company.

Efficient Computer San Francisco, California, USA Office

San Francisco Bay Area, San Francisco, California, United States

Similar Jobs

7 Minutes Ago
Easy Apply
Remote or Hybrid
United States
Easy Apply
109K-215K Annually
Junior
109K-215K Annually
Junior
Big Data • Cloud • Software • Database
Build and maintain agent skills, tooling, and evaluation infrastructure: CLIs, libraries, CI workflows, metrics, safety gates, and observability for agent behavior. Design evaluation datasets, investigate failures, and collaborate with product and security teams to ship reliable, reusable internal systems.
Top Skills: C#Ci/CdClisGithub ActionsGoJavaJavaScriptLlmsMongoDBPythonStatic AnalysisTypescript
10 Minutes Ago
Remote or Hybrid
USA
140K-215K Annually
Senior level
140K-215K Annually
Senior level
Cloud • Computer Vision • Information Technology • Sales • Security • Cybersecurity
Build and scale AI platform infrastructure for internal agents across AWS/GCP. Integrate identity (Okta, OAuth2/OIDC), implement agentic security, containerized deployments (Docker/Kubernetes), CI/CD and Terraform-based pipelines, run vendor evaluations, and design observability/telemetry for LLM-driven workflows while collaborating with security, identity, and engineering teams.
Top Skills: AWSCi/CdDockerGCPKubernetesLlmsOauth2OidcOktaPythonRest ApisTerraformTypescript
An Hour Ago
In-Office
175K-297K Annually
Mid level
175K-297K Annually
Mid level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
The role involves defining ESD and latch-up strategies, ensuring product reliability, leading validation processes, and interfacing with design and manufacturing teams.
Top Skills: Cmos DevicesEsd PhysicsEsda StandardsJedec Standards

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account