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SiTime

Principal Analog Mixed-Signal Design Engineer

Posted 22 Days Ago
Be an Early Applicant
In-Office
Santa Clara, CA, USA
165K-227K Annually
Senior level
In-Office
Santa Clara, CA, USA
165K-227K Annually
Senior level
Lead the development of analog mixed-signal ICs, supervise design, collaborate with cross-functional teams, and ensure design validation and testing for high-volume production.
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About SiTime

 

SiTime is the Precision Timing company. 


Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.


Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit:  www.sitime.com.


Responsibilities:

  • Lead development of analog Mixed-signal IC and owns the top level
  • Supervise and review block designer work and hold design review
  • Work with cross-functional team to architect the chip for DFT 
  • Closely work and support cross functional team for bench validation, qualification and final test development. 
  • Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes 
  • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications 
  • Perform transistor-level design and simulation using industry leading EDA tools 
  • Lead comprehensive design reviews 
  • Supervise Analog Circuit Physical Design Layout and edit layouts 
  • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release
  • Work closely with the verification team to define the verification matrix. 
  • Have the ownership of the top-level schematic and run all the top-level analog simulation.
  • Participate in top-level AMS verification.   

 

Qualifications & Requirements :   

  • M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of  with relevant experience in Electrical Engineering 
  • Provel track record of taking at least one analog-mixed signal part to high-volume production.
  • Proven track record at each stage of the following:
    • Circuit architecture development and technical feasibility studies 
    • Writing detailed block-level specifications and review documents 
  • Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture.
    • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL 
    • Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers 
    • Extensive experience with post-layout extraction and verifications 
    • Experience with validation, characterization, qualification, and adherence to production release criteria 
    • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers 
    • Ability to work independently and drive solutions to challenging problems 


Desired Characteristics & Attributes:

  • Strong team player

 

Compensation Range:

 

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. 


The annual base salary range for this role is $164,800.00 – $226,600.00. The final offer is determined by factors such as location, experience, education, and training.


 In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

 

Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.


SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. 

  • Innovation on Top – Philosophies of Innovation with Rajesh Vashist
  • Fabrication Knowledge – An Interview with Rajesh Vashist
  • SiTime Corporation – YouTube


 #LI-SITIME

HQ

SiTime Santa Clara, California, USA Office

5451 Patrick Henry Drive, Santa Clara, CA, United States, 95054

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