SiTime Logo

SiTime

Principal FPGA Design Engineer

Posted Yesterday
Be an Early Applicant
In-Office
Santa Clara, CA, USA
165K-227K Annually
Expert/Leader
In-Office
Santa Clara, CA, USA
165K-227K Annually
Expert/Leader
Lead the design and development of FPGA-based platforms for testing MEMS timing products, ensuring alignment across hardware and software. Provide technical leadership and mentorship while overseeing the full FPGA lifecycle.
The summary above was generated by AI

About SiTime

SiTime is the Precision Timing company. 


Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.


Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit www.sitime.com

 

Job Summary

We are seeking a seasoned FPGA Architect with a minimum of 10 years of experience to lead the design and development of FPGA-based platforms that support internal testing and validation of our precision, high-performance MEMS timing products. This role is critical to developing robust infrastructure for frequency measurement, low phase noise and low jitter characterization, production, and system-level validation

 

Responsibilities:

  • Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing
  • Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams
  • Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains
  • Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing closure, and bring-up
  • Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure
  • Champion design reviews, documentation standards, and continuous improvement practices
  • Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs
  • Act as a key technical liaison between engineering, product, and operations teams to ensure seamless integration and execution

 

Qualifications & Requirements :

  • MS in Electrical Engineering, Computer Engineering, or related field
  • 10+ years of hands-on experience in FPGA architecture and development (Xilinx, Intel/Altera, or similar)
  • Deep expertise in Verilog/VHDL, simulation tools (ModelSim, Vivado, etc.), and scripting (Python, TCL)
  • Proven track record in designing systems with low jitter, low phase noise, and high signal fidelity
  • Strong understanding of timing analysis, clock domain crossing, and high-speed interfaces (PCIe, DDR, SERDES)
  • Experience with lab bring-up, debugging tools (logic analyzers, oscilloscopes), and test automation
  • Demonstrated leadership in driving cross-functional initiatives and delivering complex technical programs
  • Excellent communication, collaboration, and stakeholder management skills 


Preferred Qualifications

  • Experience in MEMS or timing product domains
  • Familiarity with hardware/software co-design and embedded systems
  • Exposure to production test environments and ATE systems
  • Experience presenting technical strategies and outcomes to executive leadership

 

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. 


The annual base salary range for this role is $164,800.00 - $226,600.00. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

 

Benefits offered : 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

 

SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. 

  • Innovation on Top – Philosophies of Innovation with Rajesh Vashist
  • Fabrication Knowledge – An Interview with Rajesh Vashist
  • SiTime Corporation – YouTube

#LI-SITIME

HQ

SiTime Santa Clara, California, USA Office

5451 Patrick Henry Drive, Santa Clara, CA, United States, 95054

Similar Jobs

2 Days Ago
In-Office
175K-225K Annually
Expert/Leader
175K-225K Annually
Expert/Leader
Hardware • Security • Software • Cybersecurity
The Principal FPGA/RTL Design Engineer will lead projects in signal processing algorithm implementation for advanced wireless systems, requiring extensive FPGA design experience and digital signal processing expertise.
Top Skills: Fpga ImplementationMatlabPerlPythonRtl DesignVivado IdeXilinx Fpgas
130K-222K Annually
Senior level
Aerospace • Hardware • Information Technology • Security • Software • Cybersecurity • Defense
The role involves planning, architecting, and developing verification environments for FPGAs, leading teams, mentoring, and improving verification processes.
Top Skills: BitbucketC++CadenceGitJavaJIRAMatlabMentor QuestaPerlPythonSimulinkSystemverilogUvmVhdl
25 Days Ago
In-Office
165K-250K Annually
Senior level
165K-250K Annually
Senior level
Software
The Principal FPGA/RTL Design Engineer will design and implement signal processing algorithms for wireless networking, collaborating with teams on system engineering, RTL coding, FPGA synthesis, and hardware verification.
Top Skills: FpgaMatlabPerlPythonSystem-VerilogVerilogVivado IdeXilinx

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account