Hudson Information Technology and Manpower Services Logo

Hudson Information Technology and Manpower Services

RTL Engineer, Networking ASIC

Posted Yesterday
Be an Early Applicant
In-Office
San Jose, CA, USA
150K-180K Annually
Senior level
In-Office
San Jose, CA, USA
150K-180K Annually
Senior level
Design and implement RTL for high-speed networking ASICs focusing on packet buffering, queuing, scheduling, and on-chip memory subsystems. Implement and validate designs on ASIC platforms with verification, synthesis, and timing closure. Optimize pipelining and performance, support Ethernet/IP and UCIe protocols, and debug complex networking issues alongside architects, hardware, and firmware teams.
The summary above was generated by AI

Position Overview

We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s.  If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips. 

Responsibilities 

·  Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling/arbitration design.

· Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with the verification team to conduct thorough testing and validation to ensure functionality and reliability.

· Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.

·  Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high-speed interconnects such as UCIe.

· Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.

Qualifications

ME/BE with a minimum of 8-15 years of experience.

Hands-on knowledge of System Verilog and Verilog is mandatory.

Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.

Proven expertise in designing and optimizing scheduling and QoS mechanisms.

Experience with Ethernet and IP protocols.

Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.

Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences

Similar Jobs

13 Days Ago
In-Office
Saratoga, CA, USA
210K-275K Annually
Senior level
210K-275K Annually
Senior level
Artificial Intelligence • Hardware
The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.
Top Skills: Asic Design MethodologiesEthernetIp ProtocolsSystemverilogVerilog
An Hour Ago
Remote or Hybrid
Santa Clara, CA, USA
192K-337K Annually
Expert/Leader
192K-337K Annually
Expert/Leader
Artificial Intelligence • Cloud • HR Tech • Information Technology • Productivity • Software • Automation
Lead design and scaling of role architecture, competency frameworks, collaboration models, and org design governance for the Customer Excellence Group. Partner with leaders, HR, and L&D to translate strategy into practical role mandates, enable role communities, drive stakeholder alignment, and support transformation initiatives to improve organizational effectiveness across a global, matrixed SaaS organization.
Top Skills: Servicenow
An Hour Ago
Hybrid
Mountain View, CA, USA
Senior level
Senior level
Artificial Intelligence • Cloud • HR Tech • Information Technology • Productivity • Software • Automation
Design, build, and productionize scalable agentic AI systems (agent orchestration, sandboxed execution, memory, latency optimization, knowledge graphs). Implement frontier AI architectures, collaborate with ML/security/product teams, mentor engineers, and deliver production-grade code and product improvements.
Top Skills: GoJavaLlmsmacOSOpenaiPython

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account