Lead high-speed and mixed-signal PCB layout in Altium from placement through manufacturing release. Define stack-ups, impedance targets, length-matching, return-path strategies, and DFM/DFT. Collaborate with electrical, firmware, mechanical, and test teams to meet SI/PI requirements, de-risk first-pass success, and support lab bring-up and manufacturing.
Array Labs builds advanced radar systems to help humanity understand and respond to changes across the physical world.
We’re launching a coordinated fleet of radar satellites to create a high-resolution 3D map of the Earth – updated in real time – enabling faster, smarter decision-making for government and commercial organizations supporting disaster response, infrastructure resilience, and mission-critical geopolitical intelligence.
We design and build our satellites end-to-end, producing the world’s most advanced earth observation satellites. Our fleet will deliver unprecedented levels of accuracy, coverage, and responsiveness to power critical insights precisely where they’re needed most.
About the Job
As a Senior High-Speed PCB Layout Engineer, you will own the physical implementation of Array’s high-speed digital and mixed-signal electronics in Altium, translating schematics and performance requirements into layouts and functional designs. Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces.
You will partner closely with electrical design, firmware, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases. The boards you ship will directly determine signal integrity, power integrity, noise performance, and overall system reliability in the lab and on orbit.
Responsibilities:
- Own high-speed PCB layout from initial placement through manufacturing release in Altium
- Define and implement stack-ups, impedance targets, length-matching constraints, and reference plane/return-path strategies for high-speed interfaces
- Translate schematic intent into layouts that meet signal integrity and power integrity requirements across mixed-signal and digital domains
- Partner with electrical design, firmware, mechanical, and test engineers to develop layout constraints, run reviews, and de-risk first-pass success
- Drive DFM/DFT considerations with fabrication and assembly partners, including documentation and release artifacts
Basic Qualifications:
- B.S. in Electrical Engineering, or a related field with 4+ years of relevant experience
- Experience in PCB layout, fabrication, and release of high-speed digital and mixed-signal electronics
- Excellent teamwork and communication skills
- Learns new concepts rapidly, completely, and in a self-directed manner
- High levels of self-motivation and personal accountability
- Ability to work in a fast-paced environment under significant time constraints
Preferred Skills and Experience:
- Experience designing high-speed digital and mixed-signal PCB layouts including constraint-driven routing, impedance control, and length matching
- Comfort with Altium Designer for complex layout and clean manufacturing outputs; familiarity with Allegro and/or OrCAD
- Experience developing PCB stack-ups and layout constraints for high-speed interfaces and dense, high-performance boards
- A strong intuition for layout-driven SI/PI behavior, including return paths, reference plane strategy, via transitions, and noise coupling between domains
- Experience working closely with electrical design engineers to translate schematic intent into layouts that work on the first spin
- Experience with manufacturing release, DFM/DFT considerations, and collaborating with fabrication and assembly partners
- Experience supporting lab bring-up and debug alongside design and test engineers, including investigating SI/PI issues observed on hardware
- Familiarity with SI/PI analysis workflows and tools such as Ansys SIwave, Keysight Power Analyzer, HyperLynx, or Sigrity
- Experience taking high-performance hardware from prototype through qualification and environmental testing
ITAR Requirements
To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State
Equal Opportunity Employer
Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status
Interview Process
We will conduct interviews via Google Meet; the typical process takes around 2-4 weeks to complete from start to finish.
Hiring and Compensation Strategy
Our hiring and compensation strategy is simple:
1) find uncommonly good people
2) pay them uncommonly well
You can anticipate competitive pay, with high flexibility between salary and equity-based compensation.
Why Join Array Labs?
Array Labs is launching a constellation of satellites to create the first high-resolution, real-time, three-dimensional model of Earth. Our next-generation satellite technology will offer image quality 60x greater than traditional techniques, profoundly expanding humanity’s ability to understand and respond to events on a global scale.
In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.
Array Labs Palo Alto, California, USA Office
Palo Alto, CA, United States
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