Senior Photonic Design/Layout Engineer

Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of people who lack abundant and affordable internet by pioneering high-throughput, long-range free-space optical communication (FSOC). Our links use eye-safe lasers propagating between two terminals to transmit high-speed data wirelessly. Lead the charge in bringing our groundbreaking wireless optical communication to the world. Join us to light the way toward bridging the digital divide and illuminating the future.

Taara is seeking a Senior Photonic Design/Layout Engineer to work on next-generation photonic and electronic integrated modules as part of the R&D team developing cutting-edge wireless optical communication systems based on integrated optical phase arrays.

The successful candidate will own the top-level layout and coordinate the layout process of the very-large-scale photonic integrated circuits (PICs) designed at Taara. This includes interfacing with foundries and contributing to photonic design and software infrastructure for layout and verification. The role requires extensive experience in photonic tape-outs, including top-level ownership of tape-outs at commercial foundries—and deep expertise in Python, Git, and gdsfactory.

We are looking for a highly motivated individual who thrives in ambiguity, enjoys working in a small, dynamic team environment, and has a passion for solving challenging problems that lead to high-impact technological advances.

• Own and deliver record-breaking photonic integrated circuit layouts.

• Contribute to photonic design, infrastructure, and vendor management.

• Demonstrate a strong motivation to make the world a better place through technology and a desire to be part of the team making this happen.

• Ph.D. in Electrical Engineering, Applied Physics, Materials Science, or a related field.

• Five (5) or more years of relevant industry experience with demonstrated achievements in photonic layout and design.

• Extensive hands-on experience with multiple tapeouts at commercial foundries in 45nm to 180nm nodes.

• Extensive experience with top-level layout ownership, layout process management, and layout team coordination.

• Extensive experience with Design Rule Checks (DRC) and Layout Versus Schematic (LVS).

• Extensive expertise in Python, Git, and gdsfactory.

• Experience interacting with commercial foundries.

• Expertise in microelectronic layout processes and photonic/electronic layout integration strategies.

• Expertise in commercial layout verification software (Calibre or equivalent).

• Expertise in photonic simulation software (Lumerical or equivalent).

• Expertise in microelectronics layout and schematics software (Cadence or equivalent).

• Excellent communication and presentation skills, with the ability to work with senior external partners with ease.

• Hands-on experience in advancing a product from the prototype phase to the final production stage.

The US base salary range for this full-time position is $220,000 - $270,000 (inclusive of bonus at target) + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your location during the hiring process.

Onsite is preferred in Sunnyvale, CA and relocation assistance is provided.