NVIDIA is a leading provider of cutting-edge technology solutions in the semiconductor industry! We specialize in the development and enhancement of integrated circuits (ICs) for a wide range of applications, including consumer electronics, automotive, and telecommunications. Our team is dedicated to innovation, quality, and pushing the boundaries of what is possible in the world of microelectronics. We are seeking a highly skilled and motivated Product Development engineer to drive bring up of innovative SOCs through collaboration with external vendors, design and production teams.
What you'll be doing:
Serve as the primary technical interface between ATE and internal partners for test strategy, ATE bring-up, and silicon qualification, driving alignment on PDE char plan, DFT coverage & engineering FA for root-cause & preventive action.
Define & drive PDE Silicon characterization plans covering key tests (scan, mbist, IObist, functional) & features covering analog mixed-signal designs.
Ensure robust test yields are achieved going from NPI to high volume manufacturing. Test yield distractors are debugged & resolved systematically to achieve the target yields.
Finalize overall reliability QUAL stress conditions based on product usage covering embedded, commercial, industrial & automotive needs.
Drive all aspects of stress testing of silicon from wafer-level to pkg. level covering silicon+pkg level reliability qualification & testing associated with it.
Ensure Burn-in needs for the product are evaluated, supported & deployed in NPI & MP phase.
Analyze & automate aging data from HTOL/pkg. qual/DVS testing & guide the team on further debug steps for further failure analysis.
Drive true failures from reliability evaluation to closure w/ final FA report, working with FA & foundry teams.
What we need to see:
Bachelor's degree in Electrical Engineering (or equivalent experience) and 5+ years of relevant experience
Analytical and problem-solving skills, especially in solving ATE test failures with root-cause analysis.
Hands on experience of debugging chip level failures on ATE platform & drive FA to closure.
Good understanding & experience of SOC / Silicon qualifications covering exposure to HTOL, ESD/LU, HTS, TC, HAST etc.
Exposure to both Teradyne and Advantest platforms is a plus
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.NVIDIA Santa Clara, California, USA Office
2701 San Tomas Expressway, Santa Clara, CA, United States, Santa Clara
Similar Jobs
What you need to know about the San Francisco Tech Scene
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
