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Cadence Design Systems

Senior/Returnship, Signal Integrity (SI) and Power Integrity (PI) - Principal Applications Engineer

Reposted 3 Days Ago
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In-Office
San Jose, CA, USA
Senior level
In-Office
San Jose, CA, USA
Senior level
Lead technical campaigns and support sales by delivering workshops and training, utilizing expert knowledge in signal and power integrity for IC and PCB designs. Collaborate with R&D and ensure customer success through effective communication and problem-solving.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Are you looking to re-enter the workforce as an Application Engineer after taking a career break for caregiving? Please note, this is not a new college grad position.

Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program.  You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. 
In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment.  Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. 

Who is eligible to apply: 
Consider applying if you are an Application Engineering professional holding a Master’s degree in EE, CE or equivalent, who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of relevant work experience.  

The candidate will work closely with Sales Account Managers and technical field application engineers supporting technical campaigns by delivering workshops, product demonstrations, training, and onsite support. The candidate should have expert-level knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high speed signal and/or power design, signal and power integrity. Design experience and industry knowledge of Signal, Power, and Thermal analysis for IC, package, and PCB designs are required.

The candidate needs to have the ability to analyze customer's environment and evaluate appropriate engineering solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on wide range of projects. Ability to understand high-speed, high-performance signal and power integrity related issues, and work with peers and other business groups.  Able to work on-site with customers without supervision. Able to communicate effectively with Cadence R&D, Product Engineering, Marketing, Sales, and with Cadence customers. Understands customer success criteria and is committed to ensuring customer success. 

Requirements;

​Master’s or Ph.D. degree in Electrical or Electronics Engineering with 5 to 10+ years related experience. In-depth knowledge of EDA industry with strong background in Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design are required.  Candidate should have experience in Cadence Allegro platform tools including: Sigrity, Clarity, Celsius, PCB Editor, IC Package, or competitive tools in these areas.  The candidate must possess excellent written and verbal communication skills.  Ability to present and clearly articulate solutions individually, and in front of medium to large groups is essential.

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Top Skills

Cadence
Celsius
Clarity
Eda Tools
Ic Package
Pcb Editor
Sigrity
HQ

Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

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