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Intel

SOC Performance Architect

Posted 8 Days Ago
Be an Early Applicant
In-Office
Santa Clara, CA, USA
106K-200K Annually
Junior
In-Office
Santa Clara, CA, USA
106K-200K Annually
Junior
As a SOC Performance Architect, you will work with design and architecture teams to improve performance of XEON CPU and AI products, evaluate hardware features, and resolve design weaknesses.
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Job Details:

Job Description: 

Join Intel and build a better tomorrow

Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us and help us create the next generation of technologies that will shape the future for decades to come.

Do Something Wonderful

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together.

The Datacenter Power and Performance Architecture group architects products that deliver leadership performance, performance efficiency and security for traditional as well as new paradigms for data centric computing in the datacenter and edge with the right balance of leadership technologies and IPs for computing, interconnect, memory and quality delivered through the best mix of silicon, packaging and platform solutions.

As a SOC Performance Architect responsibilities will include but are not limited to:

  • You will work in dynamic team environment hand in hand with our design, validation, and architecture teams to deliver best-in-class performance and innovations across the XEON CPU and AI portfolio.
  • Determining, specifying and evaluating the viability of complex hardware features and structures and ensures that software and hardware designs interface correctly.
  • Designs framework for particular functions.
  • Defines, documents and tests processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or software compatibility.
  • Identifies, analyzes and resolves subsystem and/or SoC design weaknesses. Influences the shaping of future products by significantly contributing to the architecture used across design families.

The ideal candidate will exhibit the following

  • Experience in computer architecture, software engineering, and performance analysis.
  • Provides multilayered technical expertise for next generation initiatives.

Qualifications:

Minimum Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science with 2+ year of relevant experience, or a Master’s or PhD in the same fields.
  • Hands-on experience with SoC-level development, computer architecture, operating system, system validation, and/or related fields.
  • Exposure to system performance evaluation, power analysis, including pre/post silicon work.
  • Proficiency in programming languages (C, C++, Python), parallel programming (CUDA, MPI), and scripting languages (Bash, Shell, Ruby).

Preferred Qualifications

  • Experience in digital system design or hardware descriptive languages (Verilog and/or SystemVerilog).
  • Adaptability to adopt new methodologies, frameworks, or tools (like AI), and can keep up with evolving tech landscape.
  • Ready to learn new things and collaborate across teams from various technical domains.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations:US, California, Santa Clara, US, Texas, Austin

Business group:Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
HQ

Intel Santa Clara, California, USA Office

Robert Noyce Building, Santa Clara, CA, United States, 95052

Intel Santa Clara, California, USA Office

2200 Mission College Blvd. , Santa Clara, CA, United States, 95054

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