Responsible for designing, developing, troubleshooting and debugging PCB/package/chip thermal analysis software.
Works on extremely complex problems where analysis of situations or data requires an evaluation of intangible variance factors.
Position Requirements:
The candidate should be attending a BS, MS or PhD program in ME/EE/CS, have strong programming skills in C++, and deep familiarity with object-oriented programming methods.
Prior knowledge and experience with distributed/multi-threaded programming, numerical analysis techniques, meshing techniques, finite-element based thermal simulation, CFD analysis, and in-depth understanding of electric cooling of PCB/package/chip preferred.
Experience on automatic design optimization for thermal targets is a plus.
Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
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