Staff DFT Engineer

ABOUT THE ROLE

We are looking for a Staff DFT Engineer with 8+ years of hands-on experience in scan-based DFT implementation, including Scan Streaming Network (SSN) and IJTAG (IEEE 1687). This role focuses on end-to-end scan execution, from insertion and verification through DRC closure, coverage improvement, and final DFT signoff. The ideal candidate will own scan quality, coverage closure, and DFT signoff for complex SoC designs.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Lead hands-on scan DFT implementation, including:
• Scan insertion and stitching
• Scan Streaming Network (SSN) implementation
• IJTAG (IEEE 1687) insertion and connectivity
• Perform scan DFT verification, debug, and DFT DRC closure
• Debug and resolve scan-related DRCs, connectivity issues, and control signal problems
• Run, analyze, and debug SpyGlass DFT/RTL checks, partnering with design teams to resolve violations
• Generate, simulate, and debug ATPG scan patterns
• Analyze ATPG results and drive scan coverage improvement and closure
• Develop and validate DFT-related timing constraints (scan, shift, capture, and test modes)
• Create and maintain TCL scripts for scan insertion, ATPG setup, and coverage analysis
• Optimize scan implementations for pattern efficiency and test quality
• Support hierarchical scan integration at both block and SoC levels
• Collaborate closely with RTL and Physical Design teams to resolve scan-related issues
• Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
• Assist with ATE pattern conversion and scan debug activities

QUALIFICATIONS

• Bachelor’s degree with 8+ years of relevant experience, OR Master’s degree with 6+ years of relevant experience
• 8+ years of hands-on experience in DFT scan implementation
• Strong expertise with Siemens Tessent, including:
• Scan insertion and verification
• ATPG pattern generation and coverage analysis
• IJTAG (IEEE 1687) and SSN implementation
• Strong understanding of:
• Scan Streaming Network (SSN)
• IEEE 1149.x, IEEE 1500, and IEEE 1687 standards
• Proven ability to resolve scan DFT DRCs and drive coverage closure
• Strong TCL scripting skills for automation and flow customization
• Experience developing and validating scan and test-mode timing constraints
• Full DFT lifecycle experience, from RTL/netlist through silicon debug
• Strong debugging, ownership, and problem-solving skills
• Excellent verbal and written communication skills

PREFERRED QUALIFICATIONS

• Experience with scan compression and advanced scan architectures
• Post-silicon experience, including:
• Pattern bring-up and debug
• Silicon characterization and yield learning
• Experience mentoring junior engineers or owning DFT scan signoff

LOCATION: Santa Clara, CA, OR Orange County, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $225,000.00 - $245,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.