Develops high-speed analog ICs exceeding 100 Gbaud for optical networking products. Responsibilities span product definition, circuit design, layout, verification, bring-up, design validation, qualification, testing, characterization, and production ramp-up. The role collaborates with verification, CAD, product, test, operations, and reliability teams and supports system-level customers. Required expertise includes SiGe BiCMOS or CMOS analog design, high-frequency structures, device physics, RF wafer probing, laboratory equipment, and high-speed IC evaluation.
In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise
Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.
Nokia is seeking a Senior/Staff High-Speed Analog IC Design R&D Engineer to create innovative products in a fast-paced and collaborative team environment. The engineer will be hands-on with all phases of R&D including product definition, circuit design, layout, verification, bring-up, DVT, qualification, test and production ramp-up. As a member of a vertically-integrated team, the engineer will be directly supporting system level customers and will be closely working with product, operations and reliability teams. The self-motivated engineer must be able to anticipate problems and devise effective solutions.
Responsibilities- Responsible for developing > 100Gbaud ICs for future generation products
- In charge of many aspects of IC product development, such as design, layout, and bring-up.
- Work closely with verification, CAD, product and test engineering teams to devise and conduct DVT plans and characterization.
- Experience with High-speed analog IC designs with SiGe BiCMOS or CMOS
- Knowledge of transmission lines and other high-frequency passive structures
- A good understanding of device physics and impact on analog circuits and techniques to improve performance.
- Experience with RF wafer probing, lab equipment and evaluation of high-speed analog ICs
- Familiarity with VerilogA and CAD scripting languages (Skill, python, shell scripts) would be an asset.
- Must be a team player with good verbal and written communication skills
Education Requirements
- BS 5+ years – MS/PhD preferred
- MS 3+ years
- PhD
Similar Jobs
Artificial Intelligence • Cloud • Information Technology • Consulting
Owns complex customer-facing technical programs from presales engagement through implementation and handoff. Coordinates account, product, engineering, test, services, and leadership teams; translates requirements into plans; manages intake, prioritization, risks, dependencies, reporting, escalations, and delivery commitments. The role requires influencing without authority in a matrixed environment, improving operational processes and tooling, and communicating program status to executive stakeholders.
Top Skills:
AgileCloudIntake SystemsReporting DashboardsReporting Platforms
.png){kind=logo}
AdTech • Cloud • Digital Media • Information Technology • News + Entertainment • App development
Leads the Legal Engineering organization, overseeing engineering managers, software engineers, architects, contractors, and interns. Owns delivery, architecture, reliability, quality, integrations, and interoperability across legal technology platforms, including contract lifecycle management, document management, eBilling, intellectual property, eDiscovery, and AI workflows. Partners with Legal, Product, Cyber, and executive stakeholders while managing incidents, defects, SLAs, data integrations, and team development.
Top Skills:
Agentic WorkflowsAIApi SecurityAPIsApplication SecurityAutomated TestingCi/CdData IntegrationIamMachine LearningSaas PlatformsSecure SdlcSsoWorkflow Orchestration
Cloud • Information Technology • Productivity • Security • Software • App development • Automation
Lead Atlassian’s TDP SQL engineering team, owning people leadership, platform strategy, roadmap execution, reliability, security, compliance, incident response, technical direction, cross-functional dependencies, infrastructure economics, and operational outcomes. Build a high-performing organization and evolve a scalable managed relational database platform across multiple cloud environments while supporting enterprise requirements such as data residency, encryption, disaster recovery, and tenant isolation.
Top Skills:
Backup And RecoveryCloud InfrastructureDisaster RecoveryDistributed Relational DatabasesEncryptionMulti-Cloud InfrastructureSQLTenant Isolation
What you need to know about the San Francisco Tech Scene
San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
