Staff RTL Engineer, Packet Buffering

Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today’s AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software and systems to deliver solutions that improves AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI’s solution and value proposition have been widely validated with several hyperscalers.  

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (World’s leading micro-LED display company and developer of the first augmented reality contact lens).

We are seeking an RTL Packet Buffering to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices.

• Packet Buffering Design: Design and architect solutions for high-speed networking chips, focusing on latency optimization, and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration design.
• Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks.  Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
• Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support: Provide support for various networking protocols and standards related to input and output queues, including Ethernet.
• Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.

• ME/BE with a minimum of 8-15 years of experience.
• Working knowledge of SystemVerilog and Verilog is mandatory. Prior experience with on-chip memory subsystems.
• Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms, for high-speed networking devices.
• Experience with Ethernet protocol.
• Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Why Join Us? 

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. 

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.