Top Senior Level Perl Jobs in San Francisco Bay Area

Senior Systems Engineer role at CrowdStrike focusing on architecture and management of production systems environments. Responsible for overseeing and coordinating technical resources, analyzing and developing solutions, leading projects, and improving technical systems architecture. Requires expertise in Linux engineering, virtualization technologies, CI/CD systems, and scripting.

Join a distributed team as a senior ASIC Physical Design Engineer to develop the next generation of mining ASIC. Responsibilities include block level physical implementation, timing closure, custom cell development, and enhancing design infrastructure. Requires expertise in Synopsys ICC2/Fusion Compiler and PrimeTime, experience with chip delivery, and strong scripting skills.

Design and implement features for Fastly's Control Systems team, collaborate with internal teams, contribute to infrastructure and platform needs, participate in on-call rotation, and support critical business initiatives.

Lead the design, implementation, and maintenance of Ripple's global network infrastructure, ensuring security and scalability. Provide technical leadership, network monitoring, and mentorship to support operations.

As a CPU Implementation Lead Engineer at Apple, you will be responsible for CPU IP delivery, working with multi-functional teams to implement and validate physical design, making tradeoffs for design targets, enhancing RTL-to-GDS flow, and mentoring junior engineers.

The Designated CSE is responsible for delivering world-class customer service and expertise to customers, managing technical accounts, providing integration, consulting, training, support, and professional services. This role involves customer interaction, process optimization, and escalation management. The position reports to the Director of Technical Services and requires understanding customer business needs, proactive problem-solving, and close collaboration with other departments.

Lead and perform safety analysis of FPGA subsystems and develop features with a focus on functional safety and reliability.