The Senior SoC Design Engineer will design and implement complex SoCs, integrating high-speed interfaces and managing the ASIC implementation flow, ensuring design quality and collaboration with cross-functional teams.

The Physical Design Engineer will develop low-power, area-efficient designs, implement methodologies, collaborate with teams, and perform physical verification and analysis.

The Verification Engineer will create UVM testbenches, develop verification plans, and collaborate with design teams to ensure SoCs are functionally correct and meet project deadlines.

The Senior Engineer, DFT will implement DFT techniques, ensuring verification and closure of test coverage, while collaborating with various engineering teams for Silicon debug.

Design and layout of large-scale Silicon Photonic ICs interfacing with co-designed ASICs, ensuring opto-electronic performance and signal integrity.

The Package Design Engineer will lead semiconductor packaging design, ensuring collaboration across multiple teams for reliable, cost-effective solutions while enhancing performance metrics.

The Senior Firmware Engineer will architect and develop firmware for Celestial AI's photonic fabric, collaborating on AI platform systems and enhancing resource management and optimization.

The role focuses on leading semiconductor packaging process development and managing partnerships to ensure high volume manufacturing of AI products.

The Package Reliability Engineer will conduct reliability analysis, manage OSAT collaborations, select materials, and perform failure analysis for advanced packaging systems.

The Synthesis Engineer will develop timing constraints, manage flows for ASIC designs, perform static timing analysis, and collaborate across teams to enhance design methodology and timing sign-off.

Lead the ASIC design team overseeing development, scheduling, and resource management, ensuring designs meet performance goals and timelines.

Looking for a Staff DFT Engineer with extensive experience in scan-based DFT implementation, handling end-to-end scan execution, coverage improvement, and DFT signoff for complex SoC designs.

Drive AI product assembly processes from concept to high volume manufacturing, collaborating with foundries and managing technology development while ensuring reliability and cost efficiency.

Manage complex semiconductor programs from IP development to platform delivery. Collaborate with engineering teams, manage customer interactions, and ensure program excellence.

The Test Engineer will develop, debug, and optimize ATE and SLT test programs, analyze test data, and support new product introductions. Expertise in optics-based testing is desirable.