Jobs at Eridu AI

Lead the architecture and implementation of high-performance packet processing pipelines for networking ASICs. Collaborate with cross-functional teams on chip design, performance modeling, and validation.

Lead the design and validation of mechanical systems for high-performance computing hardware, focusing on innovation in packaging, cooling, and manufacturability.

The Hardware Engineer will design, validate, and deliver systems and sub-assemblies for AI infrastructure, collaborating across multiple teams to ensure effective product development.

The Engineering Program Manager will lead complex product development programs, manage cross-functional execution, coordinate schedules, and drive communication among teams and external partners.

The Emulation Engineer will develop and deliver emulation models, execute simulation activities, and collaborate on hardware verification and software development.

The ASIC Architect will translate system requirements into detailed architecture, guide modeling and feasibility analysis, and collaborate for seamless design implementation across teams for Eridu's networking products.

Lead DFT architecture for multi-chip systems SOC, managing test design functions and supervising ATPG generation while ensuring performance standards.

The role involves post-silicon bring-up, debugging, and validation of ASICs, focusing on diagnostic infrastructures and automation frameworks.

Lead ASIC chip design from micro-architecture to full-chip integration, emphasizing RTL development, verification collaboration, and timing closure.

Lead the simulation and analysis of AI communication workloads, optimizing performance and collaborating with customers and ASIC designers to enhance AI networking solutions.

The Physical Design Engineer will manage SOC physical assembly, design methodologies, and collaborate with engineers to optimize performance, power, and area for AI infrastructure solutions.

The role involves defining, architecting, and implementing high-speed Networking ASICs, focusing on design, testing, performance optimization, and troubleshooting for AI applications.

Seeking a Senior Power Engineer to design high-efficiency power delivery solutions for AI infrastructure, focusing on DC-DC conversion and power distribution for high-performance systems.

Lead the QA strategy for Network SDK, design test frameworks, mentor engineers, validate core SDK layers, and ensure high-quality releases.

Lead the design and development of SDK for Eridu's switch ASICs, ensuring performance and production readiness. Oversee software interfaces for dataplane operations and mentor junior engineers.

Lead the development and integration of OCP SAI with SONiC, requiring expertise in programming, SDK development, and networking protocols.

Design and prototype mechanical assemblies using SolidWorks, fabricate prototypes, perform test validation, and document procedures at a cleanroom facility.

Develop verification infrastructure, perform ASIC verification, execute simulations, analyze coverage metrics, and ensure quality assurance processes.

The role involves contributing to the development of AI infrastructure solutions that enhance performance in AI data centers, focusing on silicon, software, and system innovations.

The Substrate Layout Design Engineer will develop advanced multi-die organic flip chip modules, focusing on substrate layout, routing feasibility, and collaboration with packaging and mechanical teams for manufacturability and performance optimization.