Package Layout Design Engineer

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Position Overview

We are seeking an experienced Package Layout Design Engineer to own the physical layout and routing of large, high-density, multi-die organic packages and modules, and their associated high-speed interface boards. The role spans early routing feasibility through manufacturing release and includes high-speed serial interfaces, clock and control signals, and high-current power delivery within demanding electrical, mechanical, and fabrication constraints.

The successful candidate will work closely with package integration, ASIC, signal integrity, power integrity, mechanical, system, and manufacturing teams. This position requires strong hands-on layout capability, sound engineering judgment, and the ability to work directly with foundry, substrate, assembly, board-fabrication, and contract manufacturing partners.

Position Summary

We are seeking a Package Layout Design Engineer to support the physical layout of organic substrates and interposers for multi-die compute products. The work includes signal and power routing, bump escape, stack-up implementation, design checks, and release to manufacturing.

You will work closely with package, ASIC, signal integrity, power integrity, mechanical, and supplier teams. Candidates with hands on experience in substrate, package, interposer, or complex multilayer PCB layout are encouraged to apply.

Responsibilities

• Perform physical layout of organic substrates and interposers, including die, bump-map and netlist alignment, escape routing, signal and power routing, reference planes, via structures, and stack-up implementation.
• Develop practical routing solutions for high-speed signals and high-current power delivery.
• Support routing feasibility and work with cross-functional teams on die floorplans, I/O placement, mechanical boundaries, and package/IP interfaces.
• Apply layout constraints and coordinate with signal integrity and power integrity engineers during design implementation and review.
• Perform connectivity, DRC, DFM, and manufacturing rule checks and prepare release databases and documentation.
• Work with substrate suppliers and manufacturing partners to resolve design rule and manufacturability.
• Participate in design reviews, improve layout methods and documentation, and support related package interface board layout when needed.

Qualifications

• 5 or more years of hands-on experience with substrate, package, interposer, or complex multilayer PCB layout.
• Experience using Siemens Xpedition, or Cadence Allegro, or a similar package or board layout tool.
• Experience with high density or multilayer routing, bump escape, vias, and stack up implementation.
• Working knowledge of high-speed signal routing and/or high current power delivery.
• Understanding layout design rules, connectivity checks, DRC, DFM, and manufacturing release requirements.
• Ability to work effectively with engineering teams, suppliers, and manufacturing partners.
• Experience with multi-die or chiplet-based designs, large organic substrate and modules, supplier release, and power delivery.
• Bachelor's degree in an engineering discipline or equivalent relevant experience.

Why Join Us? 

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers. 

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. 

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.