Broadcom Logo

Broadcom

ASIC Implementation Engineer

Reposted Yesterday
Be an Early Applicant
In-Office
San Jose, CA, USA
141K-226K Annually
Expert/Leader
In-Office
San Jose, CA, USA
141K-226K Annually
Expert/Leader
Lead and participate in complex ASIC physical implementations across synthesis, DFT, floorplanning, P&R, clock and power methodology, timing closure, signal integrity, and physical verification using multiple EDA tool flows.
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Broadcom is looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal integrity and physical design checks.

Responsibilities Include:

  • Participate in large complex design implementations using the latest technology nodes, lead one or more disciplines in design closure as part of the design team. 

  • Have expertise in multiple EDA vendor solutions and be able to quickly adapt to changing requirements.

  • Participate and drive peer reviews to ensure all quality requirements are met. 

  • Work with customers and design teams across multiple geographies. 

Job Complexity/Supervision: 

  • Ability to work on complex technical projects

  • Exercises judgement in selecting methods, techniques and evaluation criteria for obtaining results.

  • Able to complete tasks with little supervision, able to lead projects and set direction for other project members. 

Experience:

  • Bachelors and 12+ years of related ASIC implementation experience. Post graduate degree in EE/CE is desirable.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000. 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

HQ

Broadcom Palo Alto, California, USA Office

Palo Alto, CA, United States

Broadcom Richmond, California, USA Office

13711 International Pl Unit 200, Richmond, British Columbia, V6V 2Z8, Canada, Richmond, Canada, V6V 2Z8

Broadcom San Francisco, California, USA Office

San Francisco, United States, 0

Broadcom San Jose, California, USA Office

1320 Ridder Park Drive, San Jose, CA, United States, 95131

Broadcom Santa Clara, California, USA Office

Santa Clara, United States, 0

Broadcom Sunnyvale, California, USA Office

190 Mathilda Pl, Sunnyvale, California, 94086-6076, United States, Sunnyvale, United States, 94086-6076

Similar Jobs

2 Days Ago
In-Office
148K-203K Annually
Senior level
148K-203K Annually
Senior level
Automotive • Internet of Things • Mobile • Semiconductor • Industrial
Develop and prototype AI/ML-driven automation for ASIC/SoC design and implementation. Collaborate with academia and cross-functional teams to apply GenAI, RL, GNNs, CNNs, and other ML methods to VLSI CAD flows, pilot solutions on real designs, and drive tool/methodology improvements for power, performance, area, and quality.
Top Skills: BitbucketC++CdcCi/CdConvolutional Neural NetworksDesignsyncEda ToolsGenaiGitGraph Neural NetworksJenkinsLlmsLow-Power FlowsLsfMakePythonRdcRecurrent Neural NetworksReinforcement LearningSdcSplunkStatic Timing AnalysisSystemverilogUnix/LinuxUpfVerilogVhdl
14 Days Ago
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Lead full-chip static timing analysis and sign-off for ASICs, develop and maintain SDC constraints for multiple modes, manage MMMC timing scenarios, implement timing ECOs, and automate flows using Tcl/Python/Perl. Collaborate with RTL, physical design, and DFT teams to resolve timing, signal integrity, and IR-drop issues while incorporating foundry derates and documenting best practices.
Top Skills: CadenceIr-Drop Aware StaMulti-Mode Multi-Corner (Mmmc)On-Chip Variation (Aocv/Pocv)PerlPythonSdcShellSignal IntegrityStatic Timing Analysis (Sta)SynopsysTcl
14 Days Ago
In-Office
San Jose, CA, USA
122K-195K Annually
Senior level
122K-195K Annually
Senior level
Software • Semiconductor • Manufacturing
Lead top-level chip floorplanning and partitioning, manage clock tree and I/O/bump planning, resolve physical-design integration and DRC/LVS/EMIR issues, collaborate with package/methodology teams, and develop/improve floorplanning methodologies and vendor/IP evaluations.
Top Skills: ChipletD2D I/ODrcEda ToolsEmirHbmHigh Speed DdrLvsPerlPythonRdlRtlSerdesTcl

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account