Neurophos Logo

Neurophos

CAD/EDA Manager

Reposted 2 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
220K-255K Annually
Senior level
In-Office
San Jose, CA, USA
220K-255K Annually
Senior level
Lead EDA tooling and physical design infrastructure for analog/mixed-signal IC teams: evaluate and deploy Cadence/Spectre/Calibre toolflows, manage PDKs and TSMC N3P/N2P enablement, architect CAD compute clusters, develop SKILL/Python/Tcl automation, manage licenses/version control, liaise with foundries/vendors, provide hands-on tape-out support, and drive methodology improvements to improve designer productivity and first-pass silicon success.
The summary above was generated by AI
About Neurophos

The demand for new datacenters and AI compute is rapidly outpacing the planet's energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry's current path isn’t going to meet the need, so we took a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world-class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.

Join us and shape the future of computing!

Position Overview

We are seeking an experienced CAD Manager to lead and manage the EDA tooling, design flows, and physical design infrastructure for our analog and mixed-signal IC design teams. In this role, you will be responsible for evaluating and deploying EDA tools, developing robust custom flows from schematic capture through tape-out, and ensuring maximum designer productivity across multiple process nodes. You will work closely with design, verification, and process engineering teams to solve the toughest implementation challenges in advanced analog design.

Location

Austin, TX or San Jose, CA. Full-time onsite position.

Key Responsibilities

EDA Tool and Flow Management

  • Evaluate, deploy, and support EDA tools, including Cadence Virtuoso, Spectre, Calibre, and related analog/custom IC toolsets.

  • Develop, maintain, and optimize design flows for schematic entry, simulation, layout, parasitic extraction (PEX), and physical verification (DRC/LVS).

  • Manage EDA tool licenses, vendor relationships, and tool upgrade cycles to ensure the design team’s productivity.

  • Implement and maintain PDK installations and updates, coordinating with foundry partners (including TSMC) for process node enablement, with specific focus on advanced technology qualification and ramp.

  • Lead CAD enablement for TSMC N3P and N2P advanced nodes, including PDK bring-up, design rule updates, fill strategy, and integration / sign-off flow alignment with TSMC requirements.

  • Interface with foundries and VCA partners to facilitate a smooth tape-out process.

Infrastructure and Automation

  • Architect and maintain the CAD computing environment, including Linux workstations, EDA servers, and LSF/grid computing clusters.

  • Develop and maintain SKILL, Tcl, Python, and shell scripts to automate repetitive CAD tasks and streamline designer workflows.

  • Manage design data integrity through version control systems (Git, Vault, ClearCase) and define backup and archive strategies.

  • Collaborate with IT to plan compute resource needs, capacity planning, and infrastructure upgrades.

Team Leadership and Collaboration

  • Act as the primary technical liaison between design teams, foundries, and EDA vendors.

  • Define and enforce CAD best practices, design methodology guidelines, and tape-out checklists.

  • Provide hands-on debug support for flow and tool issues during critical project phases and tape-out windows.

  • Drive continuous improvement initiatives to reduce design cycle time and improve first-pass silicon success rates.

Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a closely related field.

  • 8+ years of hands-on experience in analog/mixed-signal IC CAD or EDA engineering.

  • Deep expertise in Cadence Virtuoso suite (schematic, layout, ADE), Spectre/Spectre X simulation, and Cadence Virtuoso SKILL scripting.

  • Strong knowledge of physical verification tools: Mentor Calibre (DRC, LVS, PEX) and/or Synopsys IC Validator.

  • Proven experience with PDK integration and support for advanced CMOS nodes; hands-on experience with TSMC N3P and/or N2P process nodes strongly preferred.

  • Familiarity with TSMC design rule documents (DRM), analog design guidelines (ADG), and tape-out sign-off requirements for N3P/N2P.

  • Proficiency in at least two scripting languages: Python, SKILL, Tcl, or Perl.

  • Experience managing EDA tool licensing (FlexLM/RLM) and floating license optimization.

  • Strong understanding of Linux/Unix computing environments and HPC cluster management.

Preferred Skills
  • Experience with custom digital/mixed-signal flows, including OpenAccess, Virtuoso Layout Suite XL, or Virtuoso RF.

  • Familiarity with post-layout simulation (EMIR, noise, reliability) methodologies.

  • Knowledge of EM/IR analysis tools (Voltus, RedHawk) applied to analog/custom blocks.

  • Prior people management or technical lead experience in a tape-out-oriented environment.

  • Experience with high-speed I/O, SerDes, PLLs, or RF circuit design CAD flows.

  • Familiarity with configuration management tools and agile project tracking (SOS, JIRA, Confluence).

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game-changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well-being. At Neurophos, we offer:

  • 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.

  • Unlimited PTO. No rigid vacation banks, just a focus on delivery.

  • 401(k) matching and stock option opportunities to ensure our success is your success.

  • Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.

  • Personalized Benefits. Choose the plans that fit your life and take the cash back for those that don’t.

Similar Jobs

27 Minutes Ago
Easy Apply
Remote or Hybrid
Texas, USA
Easy Apply
148K-184K Annually
Junior
148K-184K Annually
Junior
Cloud • Information Technology • Security • Software • Cybersecurity
Deliver technical product presentations, gather customer technical requirements, lead product evaluations and custom configurations, design and run evaluation test plans with customers, and support proof-of-value efforts. Role requires customer visits and occasional travel; collaborate with sales to drive technical win and successful deployments.
Top Skills: DnsFirewallsRoutingTcp/IpVpnZero TrustZscaler
36 Minutes Ago
Remote or Hybrid
United States
148K-185K Annually
Senior level
148K-185K Annually
Senior level
Artificial Intelligence • Big Data • Cloud • Information Technology • Software • Big Data Analytics • Automation
Own and optimize the end-to-end marketing technology stack: roadmap, tool selection, implementations, integrations, documentation, governance, and performance metrics. Partner with IT, Sales Ops, Analytics, and Legal to ensure data flows, adoption, and ROI while supporting onboarding and ongoing optimization.
Top Skills: 6SenseAPIsLeandataMarketoPower BISalesforce
37 Minutes Ago
Hybrid
Mid level
Mid level
eCommerce • Healthtech • Pet • Retail • Pharmaceutical
Manage end-to-end non-inventory procurement for fulfillment centers, sourcing corrugate, shipping materials, consumables. Maintain ABC stocking strategy, weekly planning, daily counts, purchase requests, vendor performance, and compliance with procurement, financial, and safety standards. Collaborate with Finance and Operations, oversee staging and safe offloading, and represent Procurement in site meetings, Gemba walks, and 6S audits.
Top Skills: Erp PlatformsExcelMS OfficeProcurement SystemsSpreadsheet Analysis

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account