Leads physical design and DFT teams delivering advanced-node SoCs from RTL or netlist through GDS. Owns customer engagements, technical decisions, PPA optimization, timing and power closure, foundry and library selection, sign-off criteria, and schedule execution. Collaborates with RTL, synthesis, CAD, library, tools R&D, and customer teams while improving methodologies, AI adoption, and best practices. Requires deep expertise in digital implementation flows, backend EDA tools, advanced semiconductor nodes, scripting, and customer-facing technical leadership.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are excited to welcome highly talented Physical Design Architects and Chip Leads to join our Cadence Performance Solutions Group (PSG). Working at Cadence means collaborating with some of the industry’s brightest minds and driving innovation for the world’s most advanced companies. Through Cadence’s tools, emulation hardware, and IP products, we have supported a diverse range of customers. Enabling products in data centers, advanced driver-assistance system (ADAS) automotive and physical AI, and cutting-edge artificial intelligence verticals.
As an expert Physical Design Architect, you will engage directly with our leading-edge customers to deliver differentiated RTL-to-GDS services in advanced FinFET nodes. You will lead a talented Physical Design team with the goal of not only meeting but exceeding customers’ demanding Performance, Power, Area, and Schedule (PPAS) targets. At Cadence, our customers are at the heart of everything we do, and talented leaders like you are essential to turning this passion into tangible results.
Key Responsibilities- Serve as the technical leader for Physical Design and Design for Test teams, driving complex customer SoC projects from RTL or Netlist to GDS. These critical SoCs are targeted for markets such as data centers, automotive, and artificial intelligence.
- Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions, design trade-offs, and innovative problem solving to achieve customer PPA and schedule requirements.
- Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria to ensure the best features versus cost trade-offs.
- Collaborate with internal Cadence teams to deliver technical presentations and promote internal AI initiatives to improve quality and efficiency.
- Work closely with customer or internal RTL/Synthesis teams to ensure that key metrics are achieved efficiently prior to the physical design execution phase gate.
- Partner with Cadence tools R&D to enhance tools and methodologies to meet and surpass customer requirements.
- Document and share best practices and lessons learned from ongoing and completed projects to improve efficiency, success rates, and AI adoption in future programs
- Fifteen or more years of industry experience in Physical Design.
- Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
- Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis (including timing constraints).
- Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
- Demonstrated experience in complete design closure for chip top-level projects.
- Expertise in PPA optimization, including driving trade-offs between performance, power, and area to meet aggressive design requirements.
- Experience with advanced nodes at 7nm and below.
- Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
- Strong customer-facing communication and problem-solving skills.
- Personal drive for continuous learning and expanding professional skill sets.
- Experience in building strong technical relationships with internal stakeholders, including RTL, DFT, CAD, and Library teams.
- Master’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
- Prior experience with IC digital implementation flows and front-end EDA tools, including Synthesis, DFT, and Logical Equivalence Checking.
- Experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus, or with similar tools like ICC, ICC2, DC, or Primetime is highly desired.
- Experience with advanced nodes at 5nm and below.
- Domain expertise in CPUs, GPUs, AI Engines, Networks on Chip (NoCs), or high-speed interfaces.
- Experience with 3D IC design is a significant plus.
Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
Cadence Design Systems Santa Clara, California, USA Office
Santa Clara, United States
Cadence Design Systems Sunnyvale, California, USA Office
Sunnyvale, United States
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