CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)

About GlobalFoundries 

GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, powerefficient and highperformance solutions for highgrowth markets. GF is a trusted and holistic technology partner for customers around the world. GF’s talented, global team remains focused every day on security, longevity and sustainability. For more information, visit www.gf.com. 

New College Graduates Overview: 

We offer many full-time employment paths for recent graduates, which provide accelerated training in a fast-paced work environment, cross-functional working opportunities, and talent mobility. New college graduates are provided with mentorship, networking, and leadership opportunities, which give our new team members life-long connections and skills. 

Summary of Role: 

GlobalFoundries is seeking a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team and develop and verify advanced RISC-V processor IP. The role provides hands-on experience in CPU microarchitecture, SystemVerilog RTL implementation, functional verification, power, performance, and area analysis, automation, and debug in Austin, Texas or Santa Clara, California.
Essential Responsibilities include: 

• Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development. 

• Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts. 

• Develop verification tests, assertions, checkers, and functional coverage for CPU features. 

• Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms. 

• Support functional and coverage closure through design and verification reviews. 

• Support CPU power, performance, and area analysis and optimization. 

• Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity. 

• Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP. 
  

Other Responsibilities: 

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs. 
  

Required Qualifications: 

• Education – Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field from an accredited degree program. 

• Must have at least an overall 3.0 GPA and proven good academic standing. 

• Language Fluency - English (Written & Verbal) 

• Strong foundation in digital logic design and computer architecture. 

• Coursework, research, internship, or project experience with Verilog or SystemVerilog. 

• Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy. 

• Programming or scripting experience with Python, C/C++, or similar languages. 

• Strong analytical, problem-solving, and debugging skills. 
  

Preferred Qualifications: 

• Prior related internship or co-op experience. 

• Demonstrated prior leadership experience in the workplace, school projects, competitions, etc. 

• Project management skills, i.e. the ability to innovate and execute solutions that matter; the ability to navigate ambiguity. 

• Strong written and verbal communication skills 

• Strong planning & organizational skills 

• Knowledge of the RISC-V Instruction Set Architecture (ISA). 

• Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification. 

• CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience. 

• Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory. 

• Experience with simulation, waveform debug, Git, and Linux. 

• Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis. 

• Assembly-language programming experience. 

• Interest in using AI-assisted engineering tools to improve RTL design, verification, automation, and debug productivity. 
  

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Expected Salary Range

The exact Salary will be determined based on qualifications, experience and location.