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Cadence Design Systems

Design Engineering Intern (Summer 2025)

Sorry, this job was removed at 03:08 p.m. (PST) on Thursday, May 08, 2025
In-Office
San Jose, CA
In-Office
San Jose, CA

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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Tensilica CPU Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 Billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica CPU Processor Team is hiring interns for our R&D teams in San Jose and Austin. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.  

Design Engineering Intern positions are for one of the two roles:

(a)         Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.

(b)         Perform as a member of the Design Verification Team for Xtensa processors. Responsible for verification of microprocessor cores, multiprocessor sub-systems and their peripherals. Assist with developing test plans, writing functional assembly diagnostics, UVM/SVA monitors, debugging failures, and analyzing coverage information. Work closely with various RTL Design and Electronic Design Automation teams.

Position Requirements:

•            Currently pursuing MS/BS in Electrical Engineering, Computer Engineering, or a similar major.

•            Deep understanding of Digital Design and/or Design Verification Fundamentals

•            Excellent automation skills using Tcl, Perl, shell scripting

•            Excellent oral and written communications skills

•            Exposure to design automation tools is a plus

We’re doing work that matters. Help us solve what others can’t.

HQ

Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

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