Inabia Solutions and Consulting, Inc. Logo

Inabia Solutions and Consulting, Inc.

Design Verification Engineer

Posted 3 Days Ago
Be an Early Applicant
In-Office
Santa Clara, CA, USA
159K-318K Annually
Expert/Leader
In-Office
Santa Clara, CA, USA
159K-318K Annually
Expert/Leader
Lead development of SystemVerilog/UVM verification environments for complex SoC and networking designs. Define verification strategy, create constrained-random and coverage-driven tests, develop BFM/monitors, debug failures, automate regressions with Python/Perl/C++, and mentor junior engineers to meet tape-out schedules.
The summary above was generated by AI
About the Organization

Our client is a global leader in semiconductor and infrastructure technology, designing advanced chip solutions that power high-performance computing, networking, telecommunications, and data center systems worldwide.

The organization is at the forefront of innovation in high-speed data transfer, networking architectures, and system-on-chip (SoC) design. Its solutions are widely used across enterprise, telecom, cloud, automotive, and AI-driven industries.

With a strong focus on engineering excellence, cutting-edge research, and product reliability, the company provides an environment where engineers work on complex, large-scale systems that directly impact next-generation technologies.

Position Overview

We are seeking a Principal Design Verification Engineer to join a high-performing engineering team focused on advanced networking and SoC verification.

This role involves developing and leading functional verification environments for complex semiconductor designs, ensuring high-quality, scalable, and robust chip validation. The ideal candidate will bring deep technical expertise in verification methodologies, strong leadership experience, and the ability to work closely with design and architecture teams in a fast-paced development environment.

You will contribute to verification strategy, test planning, environment development, debugging, and cross-functional engineering collaboration.

Key ResponsibilitiesVerification Planning & Execution
  • Develop detailed verification test plans using constrained-random and coverage-driven methodologies.

  • Work closely with design teams to ensure completeness of verification requirements.

  • Define and track functional coverage metrics to ensure design quality.

Environment Development
  • Architect and build advanced verification environments using SystemVerilog and UVM.

  • Develop bus-functional models, reference models, drivers, and monitors.

  • Create scalable and reusable verification components.

Debugging & Validation
  • Develop and execute directed and random test cases.

  • Debug functional failures and collaborate with design engineers to resolve issues.

  • Perform root cause analysis of complex system-level issues.

Tool & Methodology Development
  • Develop tools and scripts to enhance verification efficiency and automation.

  • Work on regression testing frameworks and verification infrastructure.

  • Support development of scalable tools for multi-core SoC environments.

Software & Firmware Validation
  • Verify boot code and assist in firmware/software validation.

  • Develop tools and frameworks in C++, Python, or Perl for verification automation.

  • Support unit and regression testing of internal tools.

Leadership & Collaboration
  • Lead or contribute to verification efforts on complex SoC projects.

  • Work with cross-functional teams including design, architecture, and software engineering.

  • Contribute to project planning and execution under tight tape-out schedules.

  • Provide technical guidance to junior engineers where applicable.

Required QualificationsEducation & Experience
  • Bachelor’s degree in Computer Engineering, Electrical Engineering, or Computer Science.

  • 10+ years of experience in design verification, OR

  • Master’s/PhD with 5+ years of relevant experience.

Technical Skills
  • Strong expertise in SystemVerilog and UVM.

  • Experience building complex constrained-random verification environments.

  • Strong understanding of functional coverage and test planning methodologies.

  • Experience with scripting languages such as Python or Perl.

  • Experience with EDA verification tools.

  • Strong object-oriented design and programming skills.

Additional Technical Experience
  • Proficiency in C++ programming.

  • Understanding of Linux operating systems.

  • Exposure to ARM architecture and assembly language is a plus.

  • Knowledge of networking protocols is preferred.

Leadership & Soft Skills
  • Proven ability to lead verification efforts for complex SoC projects.

  • Strong debugging and problem-solving skills.

  • Ability to work independently in fast-paced environments.

  • Open-minded, collaborative, and adaptable engineering approach.

  • Strong communication skills and ability to work across teams.

Compensation & Benefits
  • Competitive salary: $158,600 – $317,800 annually

  • Full benefits package (medical, dental, vision, etc.)

  • Retirement and equity programs (as applicable)

  • Opportunity to work on cutting-edge semiconductor technologies

  • Exposure to large-scale, global engineering projects

  • High-impact role with technical leadership responsibilities

Why Join?
  • Work on next-generation semiconductor and networking technologies.

  • Contribute to high-performance SoC designs used globally.

  • Join a world-class engineering organization with strong technical depth.

  • Opportunity to lead and influence verification architecture and methodology.

  • Work in a fast-paced, innovation-driven environment focused on advanced chip design.

Similar Jobs

2 Days Ago
In-Office
99K-133K Annually
Junior
99K-133K Annually
Junior
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Design and verify ASICs and FPGAs using modern digital design flows. Implement HDL code, perform static timing and LEC/CDC/lint checks, build UVM self-checking testbenches, integrate DSP and 3rd-party IP, run hardware-in-the-loop prototypes and validate designs through hardware integration and system-level test.
Top Skills: Arm IpAsicCdcCvsEthernetFpgaGitHardware EmulationHdlJesd204CLecLintingLinuxMakePalladiumPciePerlPythonStatic Timing AnalysisSvnSystem Verilog Assertions (Sva)SystemverilogUvm
6 Days Ago
In-Office
San Jose, CA, USA
116K-246K Annually
Mid level
116K-246K Annually
Mid level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Perform full-chip functional verification for advanced memory designs; develop verification plans and SystemVerilog testbenches; apply assertions and verification techniques; collaborate with digital teams to debug; contribute to analog-digital circuit composition, circuit simulation, optimization, and floor planning across DRAM and emerging memory technologies.
Top Skills: CadenceCo-SimulationFastspiceReal-Number ModelingRtlSchematic EntrySimulationSpf ExtractionSpiceSystemverilogUnixVerilog
5 Days Ago
In-Office or Remote
7 Locations
230K-323K Annually
Senior level
230K-323K Annually
Senior level
Aerospace
Lead verification planning and execution for complex ASIC/SoC digital subsystems. Develop UVM testbenches, reference models, scoreboards, protocol monitors, and assertions. Drive coverage closure, regression health, and verification signoff. Identify corner cases, collaborate across design, systems, DFT, firmware, and physical design, and support emulation, prototyping, and post-silicon debug.
Top Skills: AssertionsBchBeamformingCdcDftDspEmulationFecFormal VerificationHigh-Speed Interface VerificationLdpcPost-Silicon DebugPrototypingRdcRtlSystemverilogUvm

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account