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Kepler

Director, Physical Design

Posted 2 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
270K-310K Annually
Expert/Leader
In-Office
San Jose, CA, USA
270K-310K Annually
Expert/Leader
Leads full-chip physical design for memory products from netlist ingestion through GDSII signoff and tapeout. Owns floorplanning, clock-tree synthesis, routing, timing closure, power-grid strategy, IR drop, electromigration, physical verification, and low-power implementation. Directs methodology, flow development, team planning, resource allocation, milestone reviews, and cross-functional integration with architecture, DFT, packaging, and manufacturing teams. Requires extensive ASIC/SoC experience, multiple successful tapeouts, advanced process expertise, and leadership in fast-paced environments.
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About the Role
We’re looking for an experienced, visionary Director of Physical Design to lead full-chip physical design for Kepler’s memory products. You’ll lead the physical design team from netlist ingestion through GDSII signoff, working closely with architecture, RTL design, DFT, packaging and manufacturing teams. You’ll be the main technical authority for physical design methodology, flows and execution. You’ll make sound VLSI trade-offs across power, performance, area, schedule and design quality in a fast-paced startup.

Key Responsibilities

  • Lead full-chip physical design from netlist to GDSII signoff for Kepler’s memory products, meeting PPA and schedule goals.

  • Own floorplanning, CTS, routing, timing closure and physical verification. Build and improve PD flows using industry-standard tools.

  • Drive team planning, resource allocation and milestone, quality and readiness reviews for successful, on-time tapeouts.

  • Work with architecture, DFT, packaging and manufacturing teams to solve complex integration problems.

  • Develop and review power grid strategies for advanced designs. Perform IR drop and electromigration (EM) analysis.

  • Partner with the DFT team on DFT-aware implementation, including scan, BIST, JTAG/boundary scan and test-mode power constraints.

  • Own DRC/LVS/ERC signoff and drive clean tapeouts across all design blocks.

Requirements

  • B.E./M.S. in Electrical Engineering, VLSI or a related field.

  • 15+ years in ASIC/SoC physical design with a proven record of successful silicon tapeouts.

  • Expert-level skill with industry-standard PD tools, flows and advanced process technologies.

  • Deep expertise in CTS, timing- and congestion-aware routing, SI-aware signoff and low-power/DFT design flows.

  • Experience implementing high-performance on-chip interconnect.

  • Experience with low-power implementation: UPF-based multi-voltage domains, power gating, retention flops, level shifters and isolation cells.

  • Strong leadership, communication and project management skills in fast-paced environments.

  • Proven record of multiple successful productizations, from physical design through post-silicon qualification and production release.

Nice to Have

  • Physical design experience with high-speed memory interfaces or memory arrays.

  • Experience with 3D innovations or advanced packaging.

  • Strong scripting and automation skills (Tcl, Python, Perl) for flow development, custom analysis and PD automation.

  • Prior startup experience: delivering high-quality results with lean teams, aggressive timelines and fast-changing product requirements.

Compensation and Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [email protected].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.

HQ

Kepler Berkeley, California, USA Office

Berkeley, CA, United States

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