Intel Logo

Intel

EDA Tools Hardware engineer

Sorry, this job was removed at 03:03 p.m. (PST) on Thursday, May 08, 2025
Be an Early Applicant
In-Office
Santa Clara, CA, USA
105K-148K Annually
In-Office
Santa Clara, CA, USA
105K-148K Annually

Similar Jobs

17 Minutes Ago
Remote or Hybrid
United States
99K-127K Annually
Senior level
99K-127K Annually
Senior level
Cloud • Insurance • Payments • Software • Business Intelligence • App development • Big Data Analytics
The Sales Enablement GTM Readiness Lead drives product readiness and launch execution, ensuring sales teams are prepared with effective messaging, utilizing AI tools for enhanced efficiency, and partnering cross-functionally to optimize go-to-market strategies.
Top Skills: AICRMLms/CmsSalesforceSeismic
23 Minutes Ago
Easy Apply
Hybrid
Easy Apply
159K-182K Annually
Mid level
159K-182K Annually
Mid level
AdTech • Artificial Intelligence • Digital Media • Marketing Tech
Design, develop, and maintain features for high traffic web services using Java and Spring. Collaborate on architecture, optimize performance, and support junior engineers.
Top Skills: AerospikeAWSCi/CdGitGradleJavaKafkaMemcachedMySQLScylladbSpring
An Hour Ago
Easy Apply
Remote or Hybrid
United States
Easy Apply
104K-204K Annually
Expert/Leader
104K-204K Annually
Expert/Leader
Big Data • Cloud • Software • Database
Lead the Talent Discovery team at MongoDB, focusing on strategic hiring through data analytics, team management, and optimal sourcing strategies.
Top Skills: AIHiring ToolsTalent Analytics

Job Details:

Job Description: 

Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Want to learn more? Visit our YouTube Channel or the links below.

 

Life at Intel

Diversity at Intel

 

 

CCG is a computing paradigm where services and data reside in scalable data centers, and those services and data can be accessed by any connected device over the Internet. Responsible for designing and optimizing processors, chipsets and other hardware for consumer devices while also working on the software ecosystem, including drivers and utilities that enhance user experience.

As an EDA Tools Hardware Engineer responsibilities include but are not limited to:

  • Designs, implements, verifies, and supports the enablement and adoption of hardware sign-off tools, flows, and methodologies.
  • Defines methodologies for hardware development related to technology node and EDA tool enabling.
  • Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, power and performance, clocking, and/or timing to enhance future TFM development.
  • Collaborates with EDA vendors on defining and early testing of next generation design sign-off tools.
  • Work closely with design teams to understand and debug static timing Analysis tool/flow/methodology issues.
  • Engage with vendors to drive tool quality improvements and fixes

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:

The candidate must have Bachelor's degree in Electrical/Computer Engineering, Computer Science or related major with 1+ years experience -OR- Master's degree in Electrical/Computer Engineering, Computer Science or related major.

1+ years experience in at lest two of the following:

  • Static timing analysis tools, flows and methodology
  • Using and debugging industry standard Static Timing Analysis tools such as Primetime, Tempus.
  • Using and debugging industry standard Power Analysis tools such as Primepower.
  • Programming in scripting languages.

Preferred Qualifications:

  • Master's degree in Electrical/Computer Engineering, Computer Science or related major and 3+ years of experience are encouraged to apply.
  • Good understanding of Digital Design, Backend automation flows and PPA optimization.
  • Good understanding of Static Timing Analysis and Power estimation/optimization tools (Primetime, Tempus.)
  • Experience using vendor tools ( Synopsys, Cadence)
  • Strong scripting/coding and problem solving skills in Perl, Python and TCL

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations:US, California, Santa Clara, US, Oregon, Hillsboro

Business group:Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$104,890.00-$148,080.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

HQ

Intel Santa Clara, California, USA Office

Robert Noyce Building, Santa Clara, CA, United States, 95052

Intel Santa Clara, California, USA Office

2200 Mission College Blvd. , Santa Clara, CA, United States, 95054

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account