FPGA DDR and IO Subsystem Architect

About Altera

Altera is a leading innovator in FPGA technology, delivering programmable solutions that power the world’s data-centric applications—from cloud and communications infrastructure to automotive, industrial, and edge AI. Our mission is to enable customers to accelerate innovation through high-performance, power-efficient, and easy-to-use FPGA platforms. At Altera, you’ll work alongside world-class engineers to architect next-generation silicon solutions that redefine performance, flexibility, and customer experience.

About the Role

As an FPGA DDR and IO Subsystem Architect, you will define and drive the architecture for next-generation high-speed external memory and general-purpose IO subsystems across Altera’s FPGA product portfolio. You will play a pivotal role in shaping differentiated memory and IO capabilities that enable industry-leading performance, power efficiency, and usability.

This is a highly visible technical leadership role requiring deep expertise in DDR and high-speed IO standards, silicon architecture, and cross-functional collaboration from early concept through production.

Responsibilities

• Develop the architecture for Altera's High-Speed External Memory Interfacing and General IO Silicon Subsystem.

• Apply deep knowledge of memory and non-memory IO applications such as DDR5, LPDDR5, MIPI, LVDS, and ONFI, as well as the competitive landscape, to architect Altera’s next-generation solutions.

• Define subsystem-level specifications and detailed micro-architecture in collaboration with circuit design, PHY, controller, packaging, signal integrity, and system teams.

• Own the solution lifecycle from early concept and feasibility analysis through silicon bring-up, validation, qualification, and production release.

• Partner closely with the Altera Quartus software team to ensure best-in-class customer usability, performance tuning, configuration, and debug capabilities.

• Drive architectural trade-off analysis across performance, power, area (PPA), cost, scalability, and reliability.

• Lead technical reviews and provide guidance across RTL design, circuit design, verification, validation, packaging, and software teams to ensure architectural intent is realized in silicon.

• Analyze competitive FPGA and ASIC IO/memory subsystem implementations to identify differentiation opportunities.

• Engage with strategic customers and ecosystem partners to understand emerging requirements and influence future product roadmaps.

Minimum Qualifications

• Bachelor’s Degree (BE) or higher in Electrical Engineering.

• 10+ years of hands-on experience in RTL design and ASIC design flows, including synthesis and static timing analysis (STA).

• Strong working knowledge of Verilog, SystemVerilog, C++, and Python.

• Deep understanding of the latest SDRAM technologies with hands-on experience in DDR4/DDR5 and/or LPDDR4/LPDDR5 controller, PHY, and subsystem design.

• Experience architecting and delivering high-speed external memory subsystems in advanced semiconductor process nodes.

• Experience in silicon architecture definition, micro-architecture development, and system-level trade-off analysis.

• Experience driving cross-functional collaboration across RTL design, circuit design, verification, validation, packaging, and software teams.

• Experience in signal integrity, power integrity, timing closure, and high-speed interface validation methodologies.

• Knowledge of general IO standards (such as MIPI, LVDS, ONFI, or similar) is desired.