Broadcom Logo

Broadcom

IC CAD Engineer

Reposted 2 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
127K-203K Annually
Expert/Leader
In-Office
San Jose, CA, USA
127K-203K Annually
Expert/Leader
The IC CAD Engineer develops and tests silicon verification decks, focusing on advanced node technologies, and is responsible for tool validation and automation.
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Broadcom Central Engineering is looking for an engineer to help with the development, installation, and testing of silicon verification decks, primarily Calibre, in support of advanced FINFET, GAA, or high voltage technologies. Experience with Calibre and Virtuoso is essential as the position will require development of test designs. Strong programming skills in PERL, TCL, SKILL and UNIX shell languages will also be necessary as the individual will be responsible for extending or possibly replacing an existing infrastructure for regression testing, currently written in PERL. Familiarity with circuit extraction and simulation would be helpful to extend regression testing also to cover extraction tool support, primarily StarRC and HSPICE, although QRC and SPECTRE familiarity is also desirable.

Knowledge of industry EDA tool availability and capabilities in these areas is expected.

Candidates must have the legal right to work in the US without visa support.

Responsibilities:

The candidate's general responsibilities include the following:

  • Development and deployment of Calibre decks for advanced FINFET/GAA/HV nodes.

  • Definition of tool acceptance and certification criteria in partnership with Broadcom teams, Foundry and EDA vendors to meet high-performance IP design needs.

  • Definition and development of IP test-cases and basic test-structures to validate tools and technology related updates on predictable schedules.

  • Development of software for automation in Skill, PERL, UNIX shell scripting and tool-flow integration.

  • Creation of documentation and hands-on training for AMS Design & Layout engineers as needed.

  • Tracking and resolution of tool and technology file issues with hands-on management per objectives of Foundry and EDA vendor support teams.

  • Monitoring of EDA industry trends and new capabilities by attending conferences and research forums. Engagement with EDA and Foundry R&D teams on advanced node capability roadmaps. Identification of new tools, development of evaluation criteria and processes and then serving as champion for introduction and usage within the Broadcom design community.

Requirements:

  • Masters in Electrical Engineering or Computer Science plus 10+ years of EDA experience. 

  • User level familiarity with related CAD Tools: Calibre, Virtuoso Layout & Schematics, Quantus QRC/StarRC/QuickCap/Raphael, and simulation using SPECTRE/HSPICE.

  • Solid background in programming skills, basic layout design, and technology knowledge to help solve layout, physical verification, and post-layout extraction challenges and problems. 

  • Experience in all phases of CAD tools from evaluation, QA, test, release, and user support to documentation.

  • Expertise in Cadence Skill, PERL, UNIX Shell and utilities.

  • Excellent interpersonal, communication, and presentation skills, along with strong multi-tasking skills, attention to detail, and the ability to work well in a team.

Additional Job Description:

Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

HQ

Broadcom San Jose, California, USA Office

1320 Ridder Park Drive, San Jose, CA, United States, 95131

Similar Jobs

2 Days Ago
In-Office
San Jose, CA, USA
127K-226K Annually
Expert/Leader
127K-226K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
The IC CAD Engineer will support and enhance CAD tools for Analog/Mixed Signal design, develop automation software, train engineers, and collaborate with EDA vendors.
Top Skills: Cadence MaestroEmxMentor Calibre/PercPerlPrimesimQuantus QrcQuickcapSkillSpectreStarrcSynopsys HspiceUnix ShellVirtuoso LayoutVirtuoso Studio 25.1Voltus-Xfi/Emir
An Hour Ago
In-Office
146K-297K Annually
Senior level
146K-297K Annually
Senior level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
Perform SI/PI analysis and modeling for HBM interposers, packages, and silicon channels. Conduct frequency- and time-domain channel characterization, mask-based timing and SPICE simulations, PDN/impedance and transient analysis, electromagnetic extraction, and automate sign-off flows with EDA vendors to ensure HBM interface reliability and product sign-off.
Top Skills: Ansys HfssAnsys SiwaveCadence PowerdcCadence PowersiCowosDdrEmibHbmInterposerKeysight AdsPciePdnSerdesSpiceSynopsys HspiceTsvUcie
An Hour Ago
In-Office
San Jose, CA, USA
83K-170K Annually
Senior level
83K-170K Annually
Senior level
Artificial Intelligence • Hardware • Information Technology • Machine Learning
The Staff Engineer will design, simulate, optimize, and verify NAND Flash circuits while collaborating on architecture evaluation and analysis for performance and reliability.
Top Skills: C++CadenceCmosHspicePerlPythonVerilog

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account