Broadcom Logo

Broadcom

IC Design Engineer (STA/ Synthesis)

Posted 22 Hours Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
Lead STA and synthesis engineering for complex SoC, ASIC, IP, digital, and mixed-signal blocks in advanced technology nodes. Responsibilities include developing and validating timing constraints, performing static timing analysis and audits, executing synthesis, defining signoff methodologies, analyzing QoR, automating workflows with Tcl or Perl, optimizing clock trees, generating timing ECOs, and driving final timing closure.
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Broadcom is looking for a lead STA/ Synthesis engineer. In this role, you will be contributing to constraint development, constraint validation, synthesis, audits (CDC, RDC, Static Equivalence, Low Power) and timing closure of mission critical IP and ASIC blocks in advanced technology nodes

Responsibilities Include:

  • Develop and validate timing constraints for intricate SoC designs.
  • Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)
  • Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocks
  • Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
  • Conduct pre-route timing checks and quality of results (QoR) analysis.
  • Automate timing analysis processes using scripting languages such as Tcl or Perl.
  • Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
  • Ensure compliance with timing signoff checklists and criteria.
  • Generate timing ECO's for timing closure
  • Drive timing closure for complex IP and ASIC blocks

Qualifications:

  • Experience with high-complexity silicon in advanced technology nodes.
  • Familiarity with timing constraint development for hierarchical designs.
  • Knowledge of clock tree planning and implementation for SoCs.
  • Experience with timing ECO creation and final timing signoff.
  • Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).
  • Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality) 
  • Strong understanding of ASIC design flows, including RTL and place-and-route.
  • Excellent problem-solving skills and attention to detail.
  • Effective communication and teamwork abilities.
  • Ability to work independently in a fast paced, cross geographical environment.
  • Direct or indirect experience with RTL/ Design is a plus
  • At a minimum Bachelors and 12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience. At this level post-graduate coursework is highly desirable

Compensation and Benefits


The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

HQ

Broadcom Palo Alto, California, USA Office

Palo Alto, CA, United States

Broadcom Richmond, California, USA Office

13711 International Pl Unit 200, Richmond, British Columbia, V6V 2Z8, Canada, Richmond, Canada, V6V 2Z8

Broadcom San Francisco, California, USA Office

San Francisco, United States, 0

Broadcom San Jose, California, USA Office

1320 Ridder Park Drive, San Jose, CA, United States, 95131

Broadcom Santa Clara, California, USA Office

Santa Clara, United States, 0

Broadcom Sunnyvale, California, USA Office

190 Mathilda Pl, Sunnyvale, California, 94086-6076, United States, Sunnyvale, United States, 94086-6076

Similar Jobs

2 Hours Ago
Hybrid
214K-290K Annually
Senior level
214K-290K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
Coordinate third-party IP delivery and lifecycle management across semiconductor programs. Track vendor commitments, procurement readiness, schedules, risks, dependencies, and recovery plans. Partner with engineering, procurement, quality, legal, finance, program management, and suppliers to resolve blockers and support leadership reporting. Improve IP lifecycle processes, reporting tools, and workflows while ensuring delivery and compliance readiness.
Top Skills: JIRASemiconductor IpSoc Development
2 Hours Ago
Hybrid
San Jose, CA, USA
196K-265K Annually
Senior level
196K-265K Annually
Senior level
Artificial Intelligence • Internet of Things • Semiconductor
The Staff Field Application Engineer drives adoption of Arm server SoCs, providing technical support, performance analysis, and training to customers while collaborating with internal teams on system integration and optimization.
Top Skills: BiosFirmwareLinuxServer SocUefi
2 Hours Ago
Hybrid
250K-338K Annually
Expert/Leader
250K-338K Annually
Expert/Leader
Artificial Intelligence • Internet of Things • Semiconductor
Designs security architectures for system-on-chip products, including root of trust, secure boot, key management, confidential computing, authentication, encryption, secure manufacturing, and device lifecycle management. Responsibilities include threat modeling, cryptographic and hardware/software security analysis, access control design, secure privilege management, isolation, attestation, and recovery mechanisms. The role also contributes to technology roadmaps and leads multinational security teams.
Top Skills: AndroidApplied CryptographyArmAttestation ProtocolsConfidential ComputingDrmIotKey ManagementSecure BootSocThreat ModelingVirtualizationWindowsX86

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account