Broadcom Logo

Broadcom

Infrastructure AI/ML Engineer for Memory Design, Characterization, and Yield Optimization

Posted 8 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
151K-241K Annually
Expert/Leader
In-Office
San Jose, CA, USA
151K-241K Annually
Expert/Leader
Lead the architecture, deployment, and scaling of agentic AI infrastructure for embedded memory design, characterization, DFT, silicon bring-up, and yield optimization. Develop multi-agent LLM workflows, integrate AI systems with EDA tools and enterprise data, automate scan-failure analysis, build predictive yield models, and establish evaluation, testing, and safety guardrails. Collaborate with memory designers, DFT experts, EDA specialists, and infrastructure engineers to deliver production-grade AI engineering solutions.
The summary above was generated by AI

Please Note:

1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

Infrastructure AI/ML Engineer for Memory Design, Characterization,

and Yield Optimization


Job Description

The Central Engineering Group is seeking an energetic, visionary, and passionate Infrastructure AI/ ML Engineer to lead the Agentic AI Infrastructure development workflow for memory design, characterization, and yield optimization.


In this role, you will collaborate with memory designers and DFT experts to build Agentic AI workflows that drive the development of state-of-the-art embedded memories optimized for PPA, DFT, and yield.


Minimum Education & Experience Qualifications

● Experience: 15+ years of progressive, relevant experience in Memory design, DFT, Silicon Yield Analysis, software architecture and AI systems engineering.

● Education: Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering.


Key Job Responsibilities

● Conceptualize, architect, deploy, and scale robust, distributed multi-agent AI frameworks tailored to transform intricate memory design workflows optimized for performance, power, area, and yield

● Orchestrate long-horizon, autonomous agent executions capable of managing multi-step reasoning, task decomposition, and decision-making across all phases of memory design development, silicon bring-up, and yield analysis

● Seamlessly integrate Large Language Model (LLM)-driven agent pipelines with core Electronic Design Automation (EDA) suites, custom in-house software tools, and enterprise data repositories.

● AI-Driven Debug: Develop and deploy ML models to automate the classification of scan failures (Chain, Stuck-at, Transition) and correlate them with design-for-test (DFT) structures.

● Predictive Yield Modeling: Integrate high-dimensional data—including Fab process parameters, PCM (Process Control Monitoring), and E-test data—to predict yield excursions before they hit the assembly line.

● Partner collaboratively with Memory Design Leads, EDA Tool Specialists, and Infrastructure Engineers to distill complex, domain-specific hardware engineering methodologies into modular, goal-driven agentic workflows.

● Align AI workflow capabilities directly with organizational efficiency targets and technical milestones across the Central Engineering Group.


Required Skillset & Technical Competencies

● Memory Design, Characterization and Yield Analysis:

● Experience designing and characterizing embedded memory in advanced technology process nodes

● Experience in compute-in-memory design and architecture

● AI Engineering & Multi-Agent Expertise:

● Experience architecting production-grade LLM applications: multi-agent orchestration,

function-calling/tool-use, and retrieval-augmented generation (RAG).

● Experience integrating agentic systems with enterprise tools, services, and knowledge sources – including building and consuming Model Context Protocol (MCP) servers, and packaging reusable agent capabilities (e.g., Agent Skills).

● Deep experience with agent orchestration frameworks such as LangGraph.

● Semiconductor Domain Knowledge & EDA Tooling:

● Fundamental grasp of chip design methodologies, IP block development lifecycles, and verification environments.

● Hands-on familiarity with industry-standard EDA tooling and frameworks

from Synopsys, Cadence, and Siemens EDA, alongside System Verilog & UVM verification environments.

● Software Engineering & Infrastructure Mastery:

● High proficiency in core programming languages and system design concepts, specifically Python and TCL.

● Expertise in microservices architecture, REST APIs, Docker, Kubernetes, Sandboxing, and config-driven workflow orchestration engine design.

● AI System Verification & Data Engineering:

● Proven experience establishing evaluation metrics, testing benchmarks, and safety guardrails for non-deterministic AI systems in high-stakes environments.

● Technical depth in Vector Databases, and cloud-native containerized orchestration pipelines.


Compensation and Benefits


The annual base salary range for this position is USD 150,800.00 To USD 241,200.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

HQ

Broadcom Palo Alto, California, USA Office

Palo Alto, CA, United States

Broadcom Richmond, California, USA Office

13711 International Pl Unit 200, Richmond, British Columbia, V6V 2Z8, Canada, Richmond, Canada, V6V 2Z8

Broadcom San Francisco, California, USA Office

San Francisco, United States, 0

Broadcom San Jose, California, USA Office

1320 Ridder Park Drive, San Jose, CA, United States, 95131

Broadcom Santa Clara, California, USA Office

Santa Clara, United States, 0

Broadcom Sunnyvale, California, USA Office

190 Mathilda Pl, Sunnyvale, California, 94086-6076, United States, Sunnyvale, United States, 94086-6076

Similar Jobs

21 Minutes Ago
Easy Apply
Remote or Hybrid
US
Easy Apply
92K-153K Annually
Mid level
92K-153K Annually
Mid level
Marketing Tech • Social Media • Software • Analytics • Business Intelligence
Manage a book of ~60 enterprise customers to drive adoption, retention, and expansion of Sprout's social media platform. Build executive relationships, run success cadences (MBRs, EBRs), surface risks, collaborate on renewals, and use data and generative AI tools to create ROI narratives and accelerate work. Partner with onboarding, professional services, and renewals to meet retention and growth KPIs.
Top Skills: ClaudeGoogle SuiteGainsightGeminiSalesforceSprout SocialTableau
2 Hours Ago
Hybrid
50K-94K Annually
Entry level
50K-94K Annually
Entry level
Artificial Intelligence • Fintech • Insurance • Marketing Tech • Software • Analytics
Investigates workers compensation and other commercial claims, determines liability and compensability, evaluates losses, estimates costs, negotiates settlements, confirms coverage, manages claim inventories, communicates with policyholders, and maintains accurate claim files and reports. The role includes comprehensive training, mentoring, and one week of onsite training in Plano, Texas, with periodic office attendance based on location.
2 Hours Ago
In-Office
99K-162K Annually
Junior
99K-162K Annually
Junior
Aerospace • Information Technology • Software • Cybersecurity • Design • Defense • Manufacturing
Develops and verifies satellite ground systems for Boeing’s MILSATCOM program. Responsibilities include requirements analysis and decomposition, systems architecture, interface design, integration and testing, verification, demonstrations, and test documentation. The role supports C2 software development in an agile environment, requirements and risk management, system-of-systems analysis, and customer delivery. This is a fully onsite position requiring an active U.S. Secret clearance and U.S. person status.
Top Skills: AgileCommand And Control (C2) SoftwareConfluenceJIRAModel Based Systems Engineering (Mbse)Requirements ManagementSystems IntegrationSystems Testing

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account