IP Design Verification Engineer

Job Details:

Job Description: 

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives.

Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products ? If so, come join us to do something wonderful.

As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs.

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

• Analytical and problem-solving skills
• Verbal/written communication skills
• Effective team player with continuous learning mindset
• Willingness to balance multiple tasks
• Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process

The primary responsibilities for this role will include, but are not limited to:

• Test bench development, directed/constrained random test generation in UVM
• Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
• Run RTL and gate level functional verification, debug failures, and analyze coverage
• Support mixed-signal verification using Verilog models of analog IP

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

• The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
• Relevant Work experience include:
  • IP or SoC verification experience using System Verilog/UVM
  • Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
  • Implementation of verification environments that include use of constrained-random stimulus
  • Code/Functional Coverage analysis
  • Writing System Verilog Assertions (SVA)

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Mixed-Signal Verification
• Experience with UCIe or PCIe or I/O

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:US, Oregon, Hillsboro

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.