Lead electrical and functional validation for next-gen DDR interfaces, automate testing with Python, and support customer technical challenges.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
- Lead cutting-edge electrical and functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM and GDDR7.
- Design and execute innovative testing strategies to accelerate post-silicon bring-up.
- Transform raw data into actionable insights through advanced analysis and visualization.
- Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams.
- Deliver high-impact characterization reports that influence product decisions and customer success.
- Automate using Python for validation, data processing, and reporting.
- Be the go-to expert for customer DDR IP challenges, ensuring rapid debug and world-class technical support.
The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Top Skills
Ddr5
Gddr7
Hbm
Lpddr5
Lpddr6
Python
Cadence Design Systems San Jose, California, USA Office
2655 Seely Avenue, San Jose, CA, United States, 95134
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