About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.
LEAD IC LAYOUT ENGINEER – Joint Development Team
The Group
The Joint Development Team (JDT) is a small, independent, cross-disciplinary group whose charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas and to collaborate with focused product development teams to get these advances to the marketplace. Current and future research areas include advanced medical devices, energy metering and fault detection, high-speed imaging, security electronics, ultra-precision references and data converters.
The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision, and of broad industrial experience. The group culture aims to foster a challenging, exciting, and supportive environment.
The team members must be comfortable working on a wide variety of products and technologies in a fast-paced and agile environment and will be exposed to various groups across the corporation’s many sites through all stages of the development cycle.
JDT is expanding its presence in the Philippines
Analog Devices’ Joint Development Team (JDT) is growing its footprint in the Philippines to enable complete front‑end product development, from architecture through first silicon. We are expanding across analog, digital, verification, and layout disciplines to support advanced mixed‑signal products in precision sensing, imaging, and security applications. This expansion represents a long‑term investment in senior technical talent and leadership roles within ADI Philippines.
The Role
The P4 Lead IC Layout Engineer is a senior technical leader responsible for driving complex IC layout development within JDT. This engineer owns layout strategy for advanced mixed signal products, influences floorplanning and architecture decisions, and serves as the primary layout authority on programs. The role has broad technical scope, high autonomy, and visible impact across projects.‑signal products, influences
This position is intended for candidates with demonstrated leadership, deep technical expertise, and the ability to raise the overall capability of the layout discipline.
Key Responsibilities:
Lead and own complex IC layout developments, including section level and toplevel layouts with full accountability for quality and schedule ‑level and top‑level layouts with full accountability for quality and schedule
Develop innovative solutions to complex layout challenges requiring deep technical analysis and expertise
Influence IC architecture, floorplanning, and partitioning decisions in collaboration with various discipline design teams
Serve as the primary technical mentor for P1–P3 layout engineers; perform reviews and capability development
Drive improvements in layout methodologies, design standards, and best practices across projects
Represent layout engineering in cross functional and program level technical discussions‑functional and program‑level technical discussions
Minimum Qualifications:
BS/MS in Electrical or Computer Engineering (or equivalent experience)
~7+ years of IC layout experience on complex analog/mixed‑signal products
Expert level proficiency in CMOS layout, parasitic management, reliability, and manufacturability ‑level proficiency in CMOS layout, parasitic management, reliability, and
Strong leadership and influence skills across design, DV, and systems teams
Excellent communication, mentoring, and technical documentation skills
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
Analog Devices Milpitas, California, USA Office
Milpitas, United States
Analog Devices San Jose, California, USA Office
3550 N 1st St, San Jose, California, 95134-1805, United States, San Jose, United States, 95134-1805
Similar Jobs
.png)
.png){kind=logo}
What you need to know about the San Francisco Tech Scene
Key Facts About San Francisco Tech
- Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
- Major Tech Employers: Google, Apple, Salesforce, Meta
- Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
- Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
- Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
- Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine
