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Cadence Design Systems

Lead Software Engineer - Low Power Verification

Posted 4 Days Ago
Be an Early Applicant
In-Office
San Jose, CA, USA
115K-213K Annually
Mid level
In-Office
San Jose, CA, USA
115K-213K Annually
Mid level
Lead development of low-power verification software for Cadence Palladium and Protium platforms. Responsibilities include enhancing UPF debugging, event logging, violation detection, IEEE 1801 support, documentation, AI-assisted debugging tools, and unified workflows across emulation and prototyping environments. The role requires collaboration with R&D, product engineering, and applications engineering teams, along with strong debugging, C++ code comprehension, RTL language knowledge, technical writing, and communication skills.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.

As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.

What you will do:

  • Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.

  • Scale UPF event logging and violation detection – apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.

  • Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples. 

  • Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.

  • Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).

  • Help consolidate and unify UPF debug across Palladium and Protium.

What we are looking for

  • BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
  • Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
  • Strong debugging skills — root-cause analysis from logs, waveforms, traces, testcases, and user reports.
  • Ability to read, review, and reason about C++ code and object-oriented designs.
  • Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
  • Strong communication and technical writing skills — able to turn scattered debug evidence into clear, user-facing workflows.

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

Cadence Design Systems Santa Clara, California, USA Office

Santa Clara, United States

Cadence Design Systems Sunnyvale, California, USA Office

Sunnyvale, United States

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