MEMS Integration Engineer

Key Responsibilities

• Product Development & Transfer: (1) Partner closely with design engineering and fabs to define, develop, and refine process flows for new MEMS products. (2) Oversee the end-to-end NPI lifecycle, from process transfer to external foundries, ensuring manufacturability and repeatability. (3) Act as the primary technical interface between nEye’s design team and foundry integration engineers.
• Foundry Process Engineering: (1) Design, document, and execute end-to-end MEMS process flows. You will integrate diverse modules (lithography, etch, thin films) into a cohesive fabrication sequence. (2) Develop and maintain rigorous process specifications, utilizing deep expertise in diverse fabrication modules including lithography, etch, and deposition to ensure seamless integration. (3) Wafer Bonding Implementation: Act as the Subject Matter Expert (SME) for back-end bonding technologies, including: anodic, fusion, eutectic, and hybrid bonding to achieve long-term hermeticity; Surface preparation and activation (plasma/chemical); Management of Thermal Expansion (CTE) mismatch and bond-induced stress. (4) TSV & 3D Integration: Lead the development and integration of Through-Silicon Vias (TSVs) for advanced device packaging. (5) Manage Foundry Tape-out activities, ensuring successful execution and alignment with project timelines. (6) Own the technical execution of the fabrication schedule, foundry activities and deliverables to ensure on-time wafer out. (7) Monitor Statistical Process Control (SPC) and address Out of Control (OOC) events immediately.
• Yield & Failure Analysis: (1) Analyze metrology data (SEM, AFM, C-SAM, IR, profilometry) to identify failure modes in the bond interface (e.g., voids, delamination) and implement corrective actions. (2) Track, analyze, and report on key process and device performance metrics, identifying opportunities for performance uplift and process simplification. (3) Lead Root Cause Analysis (RCA) and 8D reporting for process deviations or hardware failures, working closely with foundry FA labs. (4) Drive Continuous Improvement Plans (CIP) to optimize device performance, reduce unit costs, and maximize wafer yield.

Required Experience

• BS, MS, or PhD in Electrical Engineering, Mechanical Engineering, MEMS, Applied Physics, Materials Science, or a related technical field.
• 5+ years of hands-on experience in foundry process engineering, MEMS, or CMOS process development and integration.
• Product Experience: Proven track record managing tape-outs and taking products through the NPI lifecycle into high-volume manufacturing within a foundry environment.
• Process Architecture: Proven track record of architecting and executing successful, end-to-end MEMS process flows. Must demonstrate the ability to balance thermal budgets and material compatibility across complex modules.
• Advanced Wafer Bonding: Deep expertise in Wafer-to-Wafer (W2W) integration, including surface activation, alignment tolerances, and various bonding techniques (Fusion, Anodic, Eutectic, or Hybrid).
• Experience with Through-Silicon Via (TSV) integration, Cavity SOI processing, and management of TSV-induced thermo-mechanical stress in bonded wafers.
• Proficiency in SPC methodologies, yield analysis software, and a solid understanding of cleanroom practices.
• Deep familiarity using AI tools (e.g., LLMs, copilots) to accelerate engineering workflows, debugging, and problem-solving.

Preferred Experience

• Experience leading foundry-facing engineering initiatives.
• Layout & DFM: Proficiency in L-Edit, Cadence, or KLayout.
• Ability to lead Mask Floorplanning, including the strategic placement of Process Control Monitors (PCMs), alignment marks, and dicing streets.
• Mastery of quality control methods, including 6-sigma, 8D, and FMEA.
• Ability to thrive in a fast-paced, "zero-to-one" startup environment with minimal supervision.