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Intel

Platform Integration Engineer

Reposted 7 Hours Ago
Be an Early Applicant
In-Office
Santa Clara, CA, USA
122K-232K Annually
Mid level
In-Office
Santa Clara, CA, USA
122K-232K Annually
Mid level
The Platform Integration Engineer will design and develop high-performance networks-on-chip, working closely with SoC architecture teams and coordinating with the foundation IP development team.
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Job Details:

Job Description: 

Intel is seeking a Platform Integration Engineer for the Intel Chassis Group. The Chassis Group is chartered to deliver the chassis for multiple SoCs within Intel.

This Role Involves

  • Working with the SoC architecture teams to understand the SoC chassis requirements
  • Designing and developing high-performance networks-on-chip which meet the SoC PPA requirements using chassis foundation library components
  • Coordinating with the foundation IP development team within the Chassis Group to modify/create IP components as per SoC needs

Core Competencies

  • Excellent communication and collaboration skills
  • Proven ability to work effectively with global, distributed engineering teams across multiple time zones

Qualifications:

The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, or related field
  • 4+ years of hands-on experience in SoC and/or IP design

Preferred Qualifications:

  • Post Graduate Degree in Electrical Engineering, Computer Science, or related field
  • Microarchitecture, and/or fabric IP design/integration
  • Experience in Verilog/System Verilog design, along with Lint/CDC/RDC tools and timing constraint development
  • Experience with AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL interfaces
  • Proven experience analyzing power, performance, and area trade-offs in complex designs
  • Experience with physical design constraints and floorplanning considerations

          

Job Type:Experienced Hire

Shift:Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations:

Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.



Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
HQ

Intel Santa Clara, California, USA Office

Robert Noyce Building, Santa Clara, CA, United States, 95052

Intel Santa Clara, California, USA Office

2200 Mission College Blvd. , Santa Clara, CA, United States, 95054

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