Cadence Design Systems Logo

Cadence Design Systems

Principal Design Engineer

Posted Yesterday
Be an Early Applicant
In-Office
San Jose, CA, USA
112K-260K Annually
Expert/Leader
In-Office
San Jose, CA, USA
112K-260K Annually
Expert/Leader
Develops high-speed wireline communications transceivers through numerical modeling and architecture. Selects and specifies transceiver components, evaluates end-to-end system tradeoffs, collaborates with analog and digital designers, and supports laboratory characterization of completed designs. The role requires advanced mathematical modeling, communication systems, signal processing, coding, data analysis, signal propagation, circuit knowledge, and experimental skills. The position is based full-time in San Jose.
The summary above was generated by AI
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This role is for an existing vacancy.


This is an opportunity to join a dynamic and growing team of engineers developing extremely high-speed wireline communications transceivers in CMOS silicon. 

This job opening is for Numerical Modeling & Architecture, helping guide the selection and specification of transceiver components using mathematical and computer modelling techniques. 

The candidate will collaborate with analog designers, digital designers, applications engineers, and marketing specialists to help guide tradeoffs among conflicting design goals, and as such will be responsible for the performance of the end-to-end system. 

This will also require involvement in lab characterization and analysis of finally realized designs.  The position is full-time in our San Jose office.


Position Requirements:

The ideal candidate will have several of the following:

  • The ability to think through engineering systems end-to-end and identify bottlenecks and weak points.
  • Strong mathematical skills, in particular relating to linear systems (Fourier analysis, filter theory, etc.)
  • Deep knowledge of communication systems fundamentals
  • Strong coding skills for simulation and modelling, as well as data analysis
  • Good experimental skills.
  • Good knowledge of signal processing (DSP) algorithms and architecture.
  • Good working knowledge of physics of signal propagation
  • Good working knowledge of basic circuits
  • Demonstrated capacity to self-educate themselves to pick up new fields of expertise

The ideal candidate will likely have a PhD in the mathematical or physical sciences.


The annual salary range for California is $140,000 to $260,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more


The annual salary range for Canada is $112,000 to $208,000 CAD. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more

The annual salary range for California is $140,000 to $260,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

HQ

Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

Cadence Design Systems Santa Clara, California, USA Office

Santa Clara, United States

Cadence Design Systems Sunnyvale, California, USA Office

Sunnyvale, United States

Similar Jobs

4 Days Ago
In-Office
165K-210K Annually
Senior level
165K-210K Annually
Senior level
Big Data • Information Technology
Design and architect high-speed analog and mixed-signal circuits for SerDes, PHY, clocking, data conversion, references, and regulators. Lead designs from architecture through schematic, layout supervision, verification, silicon bring-up, characterization, and debug. Define test plans, collaborate across engineering functions, establish design standards, conduct technical reviews, and mentor engineers. Support advanced FinFET designs with focus on power, area, performance, signal integrity, and production tape-out.
Top Skills: AdcsAteCadence VirtuosoCmosCosmosCxlDacsEthernetFinfetLdosNvlinkPciePhyPllsSerdesSpectreUalink
20 Days Ago
In-Office
157K-227K Annually
Expert/Leader
157K-227K Annually
Expert/Leader
Artificial Intelligence • Hardware • Automation • Manufacturing
Leads high-speed data converter development, selecting circuit architectures and designing transistor-level CMOS circuits. Prepares design documentation, conducts reviews, guides layout, evaluation, and test teams, and mentors engineers. The role requires advanced electrical engineering education, extensive CMOS design experience, expertise in ADC and DAC architectures, analog circuit design, Cadence and SPICE tools, and MATLAB-based behavioral modeling. Strong communication and teamwork skills are also needed.
Top Skills: CadenceCalibration AlgorithmsCmosCurrent-Steering DacFinfetHigh-Speed Data ConvertersLdosMatlabPipeline AdcSar AdcSignal ProcessingSpice
One Month Ago
In-Office
131K-191K Annually
Senior level
131K-191K Annually
Senior level
Big Data • Cloud • Digital Media • Machine Learning • Mobile • Software • Industrial
Build and scale AI-powered design frameworks and adaptive UI components for Autodesk’s platform. Architect reusable, agent-assisted user experiences, establish processes that accelerate prototypes into production, and collaborate with engineering, product, architecture, and design stakeholders. The role also coaches designers in AI-augmented development, troubleshoots implementation challenges, and promotes scalable standards, accessibility, performance, testing, and modern frontend practices.
Top Skills: Claude CodeContextGemini Code AssistLlm-Based Coding AgentsReactReact HooksReduxTypescriptZustand

What you need to know about the San Francisco Tech Scene

San Francisco and the surrounding Bay Area attracts more startup funding than any other region in the world. Home to Stanford University and UC Berkeley, leading VC firms and several of the world’s most valuable companies, the Bay Area is the place to go for anyone looking to make it big in the tech industry. That said, San Francisco has a lot to offer beyond technology thanks to a thriving art and music scene, excellent food and a short drive to several of the country’s most beautiful recreational areas.

Key Facts About San Francisco Tech

  • Number of Tech Workers: 365,500; 13.9% of overall workforce (2024 CompTIA survey)
  • Major Tech Employers: Google, Apple, Salesforce, Meta
  • Key Industries: Artificial intelligence, cloud computing, fintech, consumer technology, software
  • Funding Landscape: $50.5 billion in venture capital funding in 2024 (Pitchbook)
  • Notable Investors: Sequoia Capital, Andreessen Horowitz, Bessemer Venture Partners, Greylock Partners, Khosla Ventures, Kleiner Perkins
  • Research Centers and Universities: Stanford University; University of California, Berkeley; University of San Francisco; Santa Clara University; Ames Research Center; Center for AI Safety; California Institute for Regenerative Medicine

Sign up now Access later

Create Free Account

Please log in or sign up to report this job.

Create Free Account