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Lattice Semiconductor

Principal Engineer Synthesis Team

Posted Yesterday
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In-Office
San Jose, CA, USA
248K-248K Annually
Expert/Leader
In-Office
San Jose, CA, USA
248K-248K Annually
Expert/Leader
Lead design and optimization of FPGA synthesis engines and toolchains. Drive QoR improvements (Fmax, area, compile time), define architecture and algorithms, modernize codebase, troubleshoot complex synthesis issues, and mentor engineers while aligning features to product roadmap.
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Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description:

Lattice Semiconductor is seeking a Principal Engineer to join the team responsible for the architecture, design, and development of advanced EDA software tools for Lattice FPGA platforms. This role is central to delivering high-quality, scalable synthesis solutions across the Lattice product portfolio, with primary ownership of the Lattice synthesis toolchain.
The ideal candidate is a technical leader and domain expert in FPGA synthesis engine design, with a deep understanding of how to achieve best-in-class results for specific FPGA architectures. You will drive industry-leading outcomes across maximum frequency (Fmax), area efficiency, runtime performance, and memory utilization—balancing tradeoffs to meet the demands of diverse customer use cases.
This role carries significant responsibility for enabling next-generation FPGA architectures, ensuring synthesis solutions scale effectively and remain competitive as the Lattice platform roadmap evolves.
Key Responsibilities
  • Provide technical leadership in the design, implementation, and optimization of FPGA synthesis engines across multiple Lattice product families
  • Collaborate with synthesis developers and cross-functional partners to define architecture, algorithms, and long-term technical direction
  • Drive quality-of-results (QoR) improvements spanning Fmax, area, and compile time
  • Lead development and enablement of new synthesis features and capabilities aligned with product roadmap priorities
  • Maintain, enhance, and modernize the synthesis codebase to ensure robustness, scalability, and long-term maintainability
  • Serve as the technical escalation point for complex synthesis issues, including customer-reported problems
  • Influence engineering best practices, code quality, and design standards within the synthesis team
  • Mentor and guide junior and mid-level engineers through design reviews and technical guidance
Required Qualifications
  • 10+ years of experience in EDA software development, with a focus on logic synthesis or place-and-route
  • Expert-level proficiency in C++, with a track record of designing, implementing, and optimizing large-scale, performance-critical software systems
  • Deep knowledge of synthesis algorithms — including technology mapping, retiming, logic optimization, and timing-driven optimization
  • Strong understanding of FPGA architectures (LUTs, DSPs, BRAMs, carry chains) and how architectural constraints inform synthesis strategy
  • Experience with QoR benchmarking methodologies and data-driven optimization workflows
  • Demonstrated ability to lead technical initiatives independently and influence without direct authority
  • Hands-on experience with generative AI tools applied to developer productivity — debugging, code review, algorithm exploration, or documentation
Preferred Qualifications
  • Familiarity with the Lattice synthesis toolchain (Radiant, Propel, or ACE environments)
  • Experience with Python scripting for automation, regression testing, or QoR analysis
  • M.S. or Ph.D. in Computer Science, Electrical Engineering, or a related field

Pay & Benefits

Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location.  Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience. 

For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location.  The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.

Base Pay Range

248400

In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.  In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more! 

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. 


Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit 
www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

 

As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.

Lattice Semiconductor San Jose, California, USA Office

2115 Onel Dr, San Jose, CA, United States, 95131

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