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Cadence Design Systems

Principal Product Engineer

Posted 17 Hours Ago
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In-Office
San Jose, CA, USA
140K-260K Annually
Senior level
In-Office
San Jose, CA, USA
140K-260K Annually
Senior level
Supports Cadence digital implementation and signoff products by debugging customer issues, collaborating with R&D, running design benchmarks, and developing implementation flows. Provides expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, signoff, hierarchical and low-power design. Requires strong analytical, communication, and automation skills using Perl, Tcl, and shell scripting.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence.   The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of  technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow. 

You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes. 

You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.  

You are an excellent communicator.

Position Responsibilities:

Support Cadence products in the Digital and Signoff team.

Track and debug customer issues and work with R&D and release team on issue resolution.

Run design benchmarks and develop flows and solutions.

Position Requirements:

MS in EE with 5+ years of experience in Digital Implementation, either as a design engineer or as a product engineer

Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.

Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.

Exposure to, and solid understanding of, hierarchical design methodologies and low power design

Energetic team player with a passion for problem solving

Strong analysis skills with a track record to prove it

Strong communication skills (verbal and written)

Automation skills using Perl, Tcl and shell scripting

The annual salary range for California is $140,000 to $260,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Cadence Design Systems San Jose, California, USA Office

2655 Seely Avenue, San Jose, CA, United States, 95134

Cadence Design Systems Santa Clara, California, USA Office

Santa Clara, United States

Cadence Design Systems Sunnyvale, California, USA Office

Sunnyvale, United States

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